Signal control device and signal control method

• US 20110264853A1
• Filed: 04/11/2011
• Published: 10/27/2011
• Est. Priority Date: 04/22/2010
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tanaka, Shinjiro
• Granted Patent: US 9,026,746 B2
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G11C 29/818 for dual-port memories
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively; an address collision detection unit detecting collision between addresses in which the first and second CPUs respectively read and write the data signal from and to the dual port RAM; a first storage unit storing the data signal read by the first CPU; a second storage unit storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM when the collision between the addresses is detected; and a switching unit switching a reading source outputting the data signal to the port to which the first CPU is connected and outputting the read data signal to the first CPU entering a readable state.

Claims

1. A signal control device comprising:

a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively;

an address collision detection unit which detects collision between an address in which the first CPU reads the data signal from the dual port RAM and an address in which the second CPU writes the data signal to the dual port RAM;

a first storage unit which stores the data signal which the first CPU reads from the dual port RAM;

a second storage unit which stores the data signal read from the address in which the second CPU writes the data signal to the dual port RAM irrespective of whether the second CPU is in a writable state, when the collision between the addresses is detected and the first CPU is not in a readable state; and

a switching unit which switches a reading source outputting the data signal to the port to which the first CPU is connected, by reading the data signal from the first storage unit when the collision between the addresses is not detected and the first CPU is in the readable state, reading the data signal from the first storage unit irrespective of whether the second CPU is in the writable state when the collision between the addresses is detected and the first CPU is not in the readable state, and reading the data signal from the second storage unit when the collision between the addresses is detected, the first CPU is not in the readable state, and the second CPU is in the writable state, and which outputs the read data signal to the first CPU entering the readable state.

2. The signal control device according to claim 1, wherein the switching unit switches between the first and second storage units reading the data signal output by the switching unit according to operation speeds of the first and second CPUs, when a timing at which the first CPU reads the data signal from the dual port RAM is the same as a timing at which the second CPU writes the data signal to the dual port RAM and thus the collision between the addresses is detected.

3. The signal control device according to claim 2, wherein the switching unit outputs the data signal written to the first or second storage unit by the first CPU when the operation timings of the first and second CPUs are the same as each other, outputs the data signal written to the second storage unit by the first CPU when the operation speed of the first CPU is faster than the operation speed of the second CPU, and outputs the data signal written to the second storage unit by the second CPU when the operation speed of the first CPU is slower than the operation speed of the second CPU.

4. The signal control device according to claim 1, wherein the switching unit switches between the first and second storage units reading the data signal output by the switching unit according to the operation speeds of the first and second CPUs, when the second CPU writes the data signal to the dual port RAM during a period in which the first CPU reads the data signal from the dual port RAM and thus the collision between the addresses is detected.

5. The signal control device according to claim 4, wherein the switching unit outputs the data signal written to the first storage unit by the first CPU when the operation timings of the first and the second CPUs are the same as each other, outputs the data signal written to the second storage unit by the first CPU when the operation speed of the first CPU is faster than the operation speed of the second CPU, outputs the data signal written to the second storage unit by the second CPU when the operation speed of the first CPU is slower than the operation speed of the second CPU and the first CPU prepares to read the data signal from the dual port RAM, and outputs the data signal written to the first storage unit by the first CPU when the operation speed of the first CPU is slower than the operation speed of the second CPU and the first CPU reads the data signal from the dual port RAM.

6. The signal control device according to claim 1, wherein the switching unit switches between the first and second storage unit reading the data signal output by the switch unit according to the operation speeds of the first and second CPUs, when the first CPU reads the data signal from the dual port RAM during a period in which the second CPU writes the data signal to the dual port RAM and thus the collision between the addresses is detected.

7. The signal control device according to claim 6, wherein the switching unit outputs the data signal written to the second storage unit by the second CPU when the operation timings of the first and second CPUs are the same as each other, outputs the data signal written to the first storage unit by the first CPU when the operation speed of the first CPU is faster than the operation speed of the second CPU and the reading is performed during preparation of the writing of the data signal, outputs the data signal written to the second storage unit by the second CPU when the operation speed of the first CPU is faster than the operation speed of the second CPU and the reading is performed during the writing of the data signal, and outputs the data signal written to the second storage unit by the second CPU when the operation speed of the first CPU is slower than the operation speed of the second CPU.

8. A signal control method comprising the steps of:

detecting, in a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively, collision between an address in which the first CPU reads the data signal from the dual port RAM and an address in which the second CPU writes the data signal to the dual port RAM;

storing the data signal which the first CPU reads from the dual port RAM in a first storage unit and storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM irrespective of whether the second CPU is in a writable state in a second storage unit, when the collision between the addresses is detected and the first CPU is not in a readable state; and

switching a reading source outputting the data signal to the port to which the first CPU is connected, by reading the data signal from the first storage unit when the collision between the addresses is not detected and the first CPU is in the readable state, reading the data signal from the first storage unit irrespective of whether the second CPU is in the writable state when the collision between the addresses is detected and the first CPU is not in the readable state, and reading the data signal from the second storage unit when the collision between the addresses is detected, the first CPU is not in the readable state, and the second CPU is in the writable state, and outputting the read data signal to the first CPU entering the readable state.