NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20110266604A1
• Filed: 12/30/2010
• Published: 11/03/2011
• Est. Priority Date: 04/30/2010
• Status: Abandoned Application

• Current Assignee: Industry-University Cooperation Foundation Hanyang University, Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Industry-University Cooperation Foundation Hanyang University, Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Suk-Goo, Lee, Seung-Beck, Oh, Seul-Ki, Lee, Jun-Hyuk
• Application Number:
  US12/982,049
• Publication Number:
  US 20110266604A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A nonvolatile memory device includes a plurality of strings each having vertically-stacked active layers over a plurality of word lines, at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape, and a plurality of bit lines each coupled to each of a plurality of active regions of the bit line connection unit.

Claims

1. A nonvolatile memory device comprising:

a plurality of strings each having vertically-stacked active layers over a plurality of word lines;

at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape; and

a plurality of bit lines each coupled to each of a plurality of active regions of the bit line connection unit.

2. The nonvolatile memory device of claim 1, wherein the each bit line is coupled to all strings of the same active layer.

3. The nonvolatile memory device of claim 1, wherein the plurality of strings are extended in the same direction as the bit lines.

4. The nonvolatile memory device of claim 1, wherein the number of stairs of the bit line connection unit having the stairway shape is equal to the number of the active layers.

5. The nonvolatile memory device of claim 4, wherein the bit line connection unit having the stairway shape is ascended stepwise in a direction toward a uppermost active region of the bit line connection unit.

6. The nonvolatile memory device of claim 4, wherein a surface area of the each stairs of the bit line connection unit having the stairway shape is the same.

7. The nonvolatile memory device of claim 1, wherein the plurality of strings is formed more than one independent block divided by at least one slit.

8. The nonvolatile memory device of claim 7, wherein the bit line connection units are symmetrically formed with respect to the slit.

9. The nonvolatile memory device of claim 1, further comprising

a plurality of bit line plugs each connected between each of active regions of the bit line connection unit having the stairway shape and each of the bit lines.

10. The nonvolatile memory device of claim 1, wherein the each of active regions of the bit line connection unit having the stairway shape is formed of a high-conductive metal or a heavily-doped N⁺ polycrystalline silicon.

11. The nonvolatile memory device of claim 10, further comprising:

a silicide layer formed between the each of the active regions of the bit line connection unit having the stairway shape and the each of the bit line plugs when the each of active regions of the bit line connection unit having the stairway shape is formed of the high-conductive metal.

12. The nonvolatile memory device of claim 1, wherein the word lines and the bit line connection unit are insulated each other.

13. A method for fabricating a nonvolatile memory device, comprising:

forming a multilayer structure having a plurality of active layers and a plurality of dielectric layers stacked alternately over a plurality of word lines;

forming at least one bit line connection unit having stairway shaped active layers by etching one end of the multilayer structure;

forming stairway shaped active regions in the bit line connection unit;

forming a plurality of bit line plugs each connected to each of the active regions of the bit line connection unit; and

forming a plurality of bit lines each connected to each of the bit line plugs.

14. The method of claim 13, wherein the forming of the stairway shaped active regions in the bit line connection unit comprises:

removing the each of the stairway shape active layers of the bit line connection unit; and

forming a high-conductive metal or a heavily-doped N⁺ polycrystalline silicon where the each removed active layers of the bit line connection unit.

15. The method of claim 14, further comprising

forming a silicide layer formed between the each of stairway shaped the active regions of the bit line connection unit and the each of the bit line plugs when the stairway shaped active regions of the bit line connection unit are formed of the high-conductive metal.

16. The method of claim 13, wherein the forming of the stairway shaped active regions in the bit line connection unit comprises

performing an ion implantation onto the each of the stairway shaped active layers of the bit line connection.

17. The method of claim 13, further comprising, after the forming of at least one bit line connection unit:

forming trenches by etching the multilayer structure; and

forming a plurality of strings by forming a tunneling insulating layer, a charge trapping layer, a blocking insulating layer, a control gate electrode over sidewalls of the trenches.

18. The method of claim 17, further comprising

forming a connection unit connected between the bit line connection unit and the plurality of strings when the forming of the trenches.

19. The method of claim 13, further comprising:

forming at least one slit dividing the multilayer structure to more than two independent blocks after the forming of at least one bit line connection unit.

20. The method of claim 19, wherein the bit line connection units are symmetrically formed with respect to the slit.

21. The method of claim 13, wherein the word lines, the bit line connection unit, and the multilayer structure are insulated each others by a lowermost dielectric layer of the multilayer structure.