MICROELECTRONIC STRUCTURE INCLUDING AIR GAP

• US 20110266682A1
• Filed: 04/29/2010
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nogami, Takeshi, Ponoth, Shom, Edelstein, Daniel C., Horak, David V., Nitta, Satyanarayana V., Huang, Elbert E., Spooner, Terry A.
• Granted Patent: US 8,288,268 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/03 Use of materials for the substrate
• CPC Class Codes: H05K 2201/0707 Shielding
• CPC Class Codes: H05K 2201/09063 Holes or slots in insulating substrate not used for electrical connections

Abstract

A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

Claims

1. A microelectronic structure comprising:

a first dielectric layer located over a substrate;

a plurality of conductor layers located embedded and planarized within the first dielectric layer and including a plurality of apertures interposed between the plurality of conductor layers;

a liner layer incompletely filling the plurality of apertures; and

a second dielectric layer located upon the liner layer and enclosing a plurality of voids interposed between the liner layer and the second dielectric layer, and separating the plurality of conductor layers.

2. The structure of claim 1 wherein the substrate comprises a bulk semiconductor substrate.

3. The structure of claim 1 wherein the substrate comprises a semiconductor-on-insulator substrate.

4. The structure of claim 1 wherein the substrate comprises a hybrid orientation substrate.

5. The structure of claim 1 wherein the plurality of voids extends within the dielectric layer deeper than the plurality of conductor layers.

6. The structure of claim 1 wherein the plurality of voids undercuts the plurality of conductor layers.

7. The structure of claim 1 further comprising a plurality of barrier layers located upon bottom and sidewall portions of the plurality of conductor layers.

8. The structure of claim 7 further comprising a plurality of capping layers aligned upon top surfaces of the plurality of conductor layers.

9. The structure of claim 1 further comprising a plurality of capping layers aligned upon top surfaces and sidewall surfaces of the plurality of conductor layers.

10. The structure of claim 8 further comprising a plurality of spacers adjoining a sidewall of the plurality of capping layers and having a thickness less than or equal to a width of the barrier layer.

11. The structure of claim 8 further comprising a plurality of spacers adjoining a sidewall of the plurality of capping layers and having a thickness greater than a width of the barrier layer.

12. A method for fabricating a microelectronic structure comprising:

forming a first dielectric layer over a substrate;

forming a plurality of conductor layers embedded and planarized within the first dielectric layer and including a plurality of apertures interposed between the plurality of conductor layers;

forming a liner layer incompletely filling the plurality of apertures; and

forming a second dielectric layer located upon the liner layer and enclosing a plurality of voids interposed between the liner layer and the second dielectric layer, and separating the plurality of conductor layers.

13. The method of claim 12 wherein the forming the second dielectric layer provides that the plurality of voids extends within the first dielectric layer deeper than the plurality of conductor layers.

14. The method of claim 12 wherein the forming the second dielectric layer provides that the plurality of voids undercuts the plurality of conductor layers.

15. The method of claim 12 wherein the forming the plurality of conductor layers includes a barrier layer upon a bottom and sidewall of the plurality of conductor layers.

16. The method of claim 15 further comprising forming a plurality of capping layers aligned upon top surfaces of the plurality of conductor layers.

17. The method of claim 12 further comprising forming a plurality of capping layers aligned upon top and sidewall surfaces of the plurality of conductor layers.

18. The method of claim 16 further comprising forming a plurality of spacers adjoining a plurality of sidewalls of the plurality of capping layers and having a thickness less than or equal to a width of the barrier layers.

19. The method of claim 16 further comprising forming a plurality of spacers adjoining a plurality of sidewalls of the plurality of capping layers and having a thickness greater than a width of the barrier layer.