Through-Substrate Vias with Improved Connections

• US 20110266691A1
• Filed: 04/28/2010
• Published: 11/03/2011
• Est. Priority Date: 04/28/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Yang, Ku-Feng
• Granted Patent: US 9,293,366 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Claims

1. A device comprising:

a substrate;

a plurality of dielectric layers over the substrate;

a plurality of metallization layers formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad;

a through-substrate via (TSV) extending from the top level of the plurality of the dielectric layers to a bottom surface of the substrate;

a deep conductive via extending from the top level of the plurality of dielectric layers to land on the metal pad; and

a metal line over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

2. The device of claim 1, wherein the metal pad is positioned lower than the top level of the plurality of metallization layers.

3. The device of claim 1, wherein the metal pad is positioned in the bottom level of the plurality of metallization layers.

4. The device of claim 1, wherein a first horizontal dimension of the TSV is greater than a second horizontal dimension of the deep conductive via.

5. The device of claim 1 further comprising an integrated circuit device at a surface of the substrate.

6. The device of claim 1, wherein the substrate is substantially free from integrated circuit devices.

7. The device of claim 1, wherein the TSV and the metal line form a continuous region formed of a same metallic material, with no barrier layer between the TSV and the metal line.

8. The device of claim 1 further comprising a barrier layer between the TSV and the metal line.

9. A device comprising:

a substrate;

an interconnect structure over the substrate, the interconnect structure comprising;

a plurality of metallization layers comprising;

a bottom metallization layer (M1);

a first metallization layer (M2) immediately over the M1;

a second metallization layer (M3) immediately over the M2;

a top metallization layer (Mtop) over the M3; and

a metal pad formed in at least one of the M1, M2, and M3;

a through-substrate via (TSV) extending from the Mtop to a bottom surface of the substrate;

a deep conductive via extending from the Mtop to the metal pad; and

a metal line overlying the interconnect structure and interconnecting the TSV and the deep conductive via.

10. The device of claim 9, wherein the metal pad is formed in the M2.

11. The device of claim 9, wherein the metal pad is formed in the M3.

12. The device of claim 9, wherein the substrate is a silicon substrate.

13. The device of claim 9, wherein the substrate is a dielectric substrate.

14. The device of claim 9, wherein the TSV and the metal line are formed of a same metallic material, with no diffusion barrier layer between the TSV and the metal line.

15. The device of claim 9 further comprising a diffusion barrier layer between the TSV and the metal line.

16. The device of claim 9, wherein a ratio of a first horizontal dimension of the TSV to a second horizontal dimension of the deep conductive via is greater than about 1.2.

17. A device comprising:

a substrate;

an interconnect structure over the substrate, the interconnect structure comprising;

a plurality of low-k dielectric layers;

a plurality of metallization layers in the plurality of low-k dielectric layers and comprising metal pads, wherein the metal pads comprises copper; and

a dielectric layer over the plurality of metallization layers, wherein a k value of the dielectric layer is higher than k values of the plurality of low-k dielectric layers;

a through-substrate via (TSV) extending from a top surface of the dielectric layer to a bottom surface of the substrate;

a first deep conductive via extending from the top surface of the dielectric layer to land on a first metal pad in a first one of the plurality of metallization layers;

a second deep conductive via extending from the top surface of the dielectric layer to land on a second metal pad in a second one of the plurality of metallization layers different from the first one; and

a metal line over the dielectric layer and electrically coupling the TSV to the first and the second deep conductive vias.

18. The device of claim 17, wherein the dielectric layer is formed of a non-low-k dielectric material.

19. The device of claim 17, wherein the TSV and the first and the second deep conductive vias form a continuous region with no diffusion barrier layer separating the TSV from the first and the second deep conductive vias.