METHOD AND SYSTEM TO VERIFY THE RELIABILITY OF ELECTRONIC DEVICES

• US 20110267081A1
• Filed: 11/26/2009
• Published: 11/03/2011
• Est. Priority Date: 12/29/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Ricci, Raffaele
• Granted Patent: US 9,018,965 B2
• Time in Patent Office: Days
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/002 where the device under test is an electronic circuit
• CPC Class Codes: G01R 31/2849 Environmental or reliability testing, e.g. burn-in or validation tests of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855

Abstract

To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted.

Claims

1-9. -9. (canceled)

10. A method of testing an electronic circuit comprising:

operating the electronic circuit while exposing the electronic circuit to electrical overstresses;

monitoring operation of the electronic circuit after exposure to the electrical overstresses;

11. The method of claim 10, wherein exposing the electronic circuit to the electrical overstresses comprises exposing at least one of a power supply and an input/output line of the electronic circuit to the electrical overstresses.

12. The method of claim 10, further comprising synchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

13. The method of claim 10, further comprising asynchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

14. The method of claim 10, further comprising generating the electrical overstresses as electrical pulses.

15. The method of claim 14, wherein at least one of amplitudes and durations of the electrical pulses are settable.

16. A method of testing an electronic circuit comprising:

exposing the electronic circuit to electrical overstresses while the electronic circuit is not operating;

monitoring operation of the electronic circuit after exposure to the electrical overstresses.

17. The method of claim 16, wherein exposing the electronic circuit to the electrical overstresses comprises exposing at least one of a power supply and an input/output line of the electronic circuit to the electrical overstresses.

18. The method of claim 16, wherein exposing the electronic circuit to the electrical overstresses comprises exposing at least one of a power supply and an input/output line of the electronic circuit to the electrical overstresses.

19. The method of claim 16, further comprising generating the electrical overstresses as electrical pulses.

20. The method of claim 19, wherein at least one of amplitudes and durations of the electrical pulses are settable.

21. A method of testing an electronic circuit comprising:

operating the electronic circuit while exposing at least one of a power supply and an input/output line thereof to electrical overstresses; and

monitoring operation of the electronic circuit after exposure to the electrical overstresses;

the electrical overstresses comprising electrical pulses having at least one of a settable amplitude and a settable duration.

22. The method of claim 21, further comprising synchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

23. The method of claim 21, further comprising asynchronously applying test stimuli to the electronic circuit while exposing the electronic circuit to the electrical overstresses.

24. A system for testing an electronic circuit comprising:

a motherboard to be coupled to the electronic circuit;

a daughterboard to be coupled to the motherboard and to expose the electronic circuit to electrical overstresses while the electronic circuit is operating; and

a circuit monitor to monitor operation of the electronic circuit after exposure thereof to the electrical overstresses.

25. The system claim 24, wherein the electronic circuit has at least one of a power supply and an input/output line;

and wherein the daughterboard exposes the electronic circuit to the electrical overstresses by exposing at least one of the power supply and the input/output line to the electrical overstresses.

26. The system of claim 24, wherein the motherboard is to synchronously apply test stimuli to the electronic circuit while the daughter board exposes the electronic circuit to the electrical overstresses.

27. The system of claim 24, wherein the motherboard is to asynchronously apply test stimuli to the electronic circuit while the daughter board exposes the electronic circuit to the electrical overstresses.

28. The system of claim 24, wherein the daughterboard is to generate the electrical overstresses as electrical pulses.

29. The system of claim 28, wherein the daughterboard is to allow setting of at least one of amplitudes and durations of the electrical pulses.

30. A system for testing an electronic circuit comprising:

a motherboard to be coupled to the electronic circuit;

a daughterboard to be coupled to the motherboard and to expose the electronic circuit to electrical overstresses while the electronic circuit is not operating; and

a circuit monitor to monitor operation of the electronic circuit after exposure thereof to the electrical overstresses.

31. The system of claim 30, wherein the electronic circuit has at least one of a power supply and an input/output line;

and wherein the daughterboard exposes the electronic circuit to the electrical overstresses by exposing at least one of the power supply and the input/output line to the electrical overstresses.

32. The system of claim 30, wherein the daughterboard is to generate the electrical overstresses as electrical pulses.

33. The system of claim 32, wherein the daughterboard is to allow setting of at least one of amplitudes and durations of the electrical pulses.