TEST CIRCUIT OF AN INTEGRATED CIRCUIT ON A WAFER

• US 20110267086A1
• Filed: 04/25/2011
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto
• Granted Patent: US 8,941,401 B2
• Time in Patent Office: Days
• US Class Current: 324/754.21
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.

Claims

1. A testing device, comprising:

a first test antenna configured to form a wirelessly loopback connection with a first embedded antenna of a semiconductor wafer to facilitate testing of the first embedded antenna by transforming an electromagnetic signal between the first test antenna and the first embedded antenna into an electrical signal; and

a second test antenna configured to form a wirelessly loopback connection with a second embedded antenna of the semiconductor wafer to facilitate testing of the second embedded antenna by transforming an electromagnetic signal between the second test antenna and the second embedded antenna.

2. The testing device of claim 1 wherein said first and second test antennas are configured to exchange radio frequency (RF) signals of an irradiated type, with said first and second embedded antennas, and to transmit RF signals inside the testing device between said test antennas.

3. The testing device of claim 1 wherein said first and second test antennas are interconnected through at least one transmission line or circuit network.

4. The testing device of claim 3 wherein said transmission line or circuit network crosses a scribe line of separation between a first and a second integrated circuit comprising said first and second embedded antennas.

5. The testing device of claim 1, comprising a conductive layer above a passivation layer of said wafer comprising said at least one integrated circuit, said conductive layer configured to form a closed loop surrounding said first and second embedded antennas.

6. The testing device of claim 5 wherein said conductive layer covers at least one of a first and of a second integrated circuit comprising said first and second test antennas.

7. The testing device of claim 5 wherein said conductive layer is realized in part inside and in part outside at least one of a first and of a second integrated circuit comprising said first and second test antennas.

8. The testing device of claim 1, comprising at least one additional pad coupled to at least one of the test antennas and configured to be contacted by at least one probe of the testing device.

9. The testing device of claim 1, comprising at least one first and one second additional pad added in a scribe line of separation of a first and of a second integrated circuit comprising said first and second test antennas.

10. The testing device of claim 1, comprising at least one first and one second additional pad in an area of one of a first and of a second integrated circuit comprising said first and second test antennas.

11. The testing device of claim 1, further comprising an ATE antenna configured to communicate with said test antennas.

12. The testing device of claim 11, comprising a supplementary antenna configured to communicate with said test antennas and with said ATE antenna.

13. The testing device of claim 11 wherein said ATE antenna is coupled to a transmitter associated with at least one of a core of magnetic material and a material with a high dielectric constant.

14. The testing device of claim 1 wherein the first and second test antenna are outside a wafer portion whereon a first and a second integrated circuit are integrated, said circuits comprising said first and second embedded antennas.

15. The testing device of claim 1 wherein the first and second antennas are housed in a probe card of said testing device.

16. The testing device of claim 15 wherein said probe card comprises said test antennas, which are coupled together through at least one of a transmission line and a circuit network and are associated with respective cores of magnetic material or a material with a high dielectric constant.

17. The testing device of claim 16 wherein said probe card comprises a single test antenna configured to wirelessly couple with said first and second embedded antennas.

18. The testing device of claim 1 wherein the first and second embedded antennas each comprise a magnetic dipole and the first and second test antennas have a planar structure in a single level of conductive material that surrounds with a closed loop said first and second embedded antennas.

19. The testing device of claim 1 wherein the first and second embedded antennas each comprise a hertzian dipole, each embedded antenna being coupled to a respective receiver/transmitter, wherein said test antennas each have a hertzian dipole, facing a respective embedded antenna with hertzian dipole, and are coupled to at least one of a transmission line or circuit network.

20. The testing device of claim 1 wherein the first and second embedded antennas are of a capacitive type and the first and second testing antennas comprise one strip of conductive material that overlaps at least in part onto said first and second embedded antennas of the capacitive type.

21. The testing device of claim 20 wherein the strip of conductive material is configured to form an ATE antenna with a magnetic dipole.

22. The testing device of claim 1 wherein the first and second embedded antennas are of a capacitive type and are above a passivation layer of said wafer, and the first and second testing antennas comprise a strip of conductive material positioned so as not to overlap on the first and second embedded antennas and to be near enough to exploit edge capacitive effects.

23. The testing device of claim 22 wherein the strip of conductive material is configured to form an ATE antenna with a magnetic dipole.

24. An integrated circuit, comprising:

at least one embedded antenna;

at least a residual portion of a first testing device configured to form a wirelessly loopback connection with the first embedded antenna to transform an electromagnetic signal between the first testing device and the first embedded antenna into an electrical signal.

25. The integrated circuit of claim 24 wherein said at least a residual portion of said first testing device comprises at least one pad configured to be used in successive processing steps after said integrated circuit is singled from a wafer.

26. The integrated circuit of claim 24 wherein said embedded antenna is of a capacitive type and said at least a residual portion of said testing device comprises at least a residual portion of a strip of conductive material coupled to a corresponding transceiver/transponder and configured to form a capacitive hertzian dipole.

27. The integrated circuit of claim 24 wherein said at least a residual portion comprises at least a residual portion of a strip of conductive material, the integrated circuit further comprising a ground plane configured to form a patch antenna with said at least a residual portion of said strip of conductive material.

28. The integrated circuit of claim 24 wherein the at least a residual portion comprises a first test antenna and a residual portion of a metallic path, the residual portion of the metallic path extending from the first test antenna up to a scribe line of said integrated circuit.

29. A method, comprising:

testing a semiconductor wafer comprising at least a first integrated circuit having a first embedded antenna by,

coupling probes of a probe card to contact pads of the semiconductor wafer;

forming a wireless loopback connection between the first embedded antenna and a first test antenna;

transmitting an electromagnetic signal between the first embedded antenna and the first test antenna; and

transforming the electromagnetic signal into an electrical signal.

30. The method of claim 29, further comprising:

embedding at least a portion of the first test antenna in the first integrated circuit prior to the testing.

31. The method of claim 30, further comprising:

subsequently separating the wafer into a plurality of integrated circuits.

32. A system, comprising:

a testing device having a faraday cage and configured to communicatively couple to at least one integrated circuit of a semiconductor wafer; and

at least one testing antenna configured to form a wireless loopback connection with at least one embedded antenna of the wafer when the testing device is communicatively coupled to the at least one integrated circuit of the semiconductor wafer.

33. The system of claim 32 wherein the at least one testing antenna comprises a plurality of testing antennas configured to form wireless loopback connections with respective embedded antennas of the semiconductor wafer when the testing device is communicatively coupled to the at least one integrated circuit of the semiconductor wafer.

34. The system of claim 33 wherein the plurality of testing antennas are embedded in respective integrated circuits of the wafer.

35. The system of claim 32 wherein the at least one testing antenna is integrated into a probe head of the testing device.

36. The system of claim 32 wherein the at least one testing antenna is embedded in the semiconductor wafer.

37. The system of claim 32 wherein the at least one testing antenna is at least partially embedded in the semiconductor wafer.

38. The system of claim 32 wherein the faraday cage comprises a plurality of probes configured to couple to a plurality of contact pads of the semiconductor wafer to electrically couple the testing device to the at least one integrated circuit of the semiconductor wafer.