Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC

• US 20110267127A1
• Filed: 01/31/2011
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: Park, Min, Staszewski, Robert Bogdan
• Granted Patent: US 8,675,725 B2
• Time in Patent Office: Days
• US Class Current: 327/306
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals
• CPC Class Codes: H03M 1/822 using pulse width modulation
• CPC Class Codes: H04B 14/026 using pulse time characteristics modulation, e.g. width, position, interval

Abstract

An integrated circuit comprises a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA. The PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.

Claims

1. An integrated circuit comprising:

a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and

a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA;

wherein the PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.

2. The integrated circuit of claim 1 wherein the integrated circuit comprises a radio-frequency digital-to-amplitude converter (RF-DAC) comprising the DPA, wherein the RF-DAC comprises at least one clock input for receiving a digital carrier signal and at least one data input for receiving an input digital envelope signal.

3. The integrated circuit of claim 1 wherein the plurality of selectable switching devices comprises an array of digitally-controlled switches coupled to both a first clock input and a first data input, wherein a first portion of the array of digitally-controlled switches is arranged to generate the envelope of the RF carrier output from the DPA with an amplitude substantially proportional to a signal at the first data input and wherein a second portion of the array of digitally-controlled switches is arranged to generate an additive RF signal to be added to the envelope of the RF carrier via the PWM signal.

4. The integrated circuit of claim 1 wherein the PWM generator comprises a delay controller arranged to control a delay of the PWM control signal that controls the PWM signal adjusting the envelope RF carrier output from the DPA.

5. The integrated circuit of claim 1 wherein the PWM generator comprises a plurality of inverters, a number of which are dynamically selected to set a pulse width of the PWM control signal provided to the subset of the plurality of selectable switching devices such that the PWM signal adjusts the envelope output RF carrier output from the DPA.

6. The integrated circuit of claim 1 wherein the PWM signal is added to the envelope RF carrier output from the DPA to control a signal timing of the DPA.

7. The integrated circuit of claim 1 wherein the PWM generator provides the PWM control signal to the subset of the plurality of the selectable switching devices such that either a centered PWM signal or a non-centered PWM signal adjusts the envelope RF carrier output from the DPA dependent upon a relative pulse position of the input signal to the DPA.

8. The integrated circuit of claim 7 further comprising a pulse center module arranged to adjust a delay of a main clock signal employed by the integrated circuit to control the relative pulse position of the centered PWM signal.

9. The integrated circuit of claim 1 further comprising a memory operably coupleable to the PWM generator and arranged to store a plurality of amplitude and/or phase parameters associated with dynamically generating a non-centered PWM signal.

10. The integrated circuit of claim 9 wherein the memory is arranged to store a plurality of amplitude and/or phase predistortion parameters associated with the PWM control signal, such that the PWM signal is predistorted based on at least one of the plurality of amplitude and/or phase predistortion parameters.

11. The integrated circuit of claim 7 wherein the PWM generator is arranged to generate a dynamically non-centered incremental PWM signal when a baseband amplitude of a phase-modulated RF carrier has a limited peak-to-minimum ratio.

12. The integrated circuit of claim 1 wherein the subset of switching devices is/are activated for a limited period of time within a radio frequency burst of a DPA transmission.

13. The integrated circuit of claim 12 wherein the subset of switching devices is/are activated during a positive half-cycle of a RF period within the radio frequency burst of the DPA transmission.

14. The integrated circuit of claim 9 further comprising a multiplier operably coupled to the memory that comprises at least two sub-memory elements, such that a first memory is responsive to an integer word of an amplitude signal to be applied to the DPA to produce a first

15. The integrated circuit of claim 9 wherein the memory is additionally arranged to store polar co-ordinate data associated with the DPA.

16. The integrated circuit of claim 1 wherein the DPA is capable of controlling an envelope of a phase-modulated RF carrier.

17. A method of controlling an envelope of a radio frequency (RF) carrier output from a digitally-controlled power generation stage (DPA) comprising a plurality of selectable switching devices, the method comprising:

generating a pulse width modulator (PWM) control signal;

selecting a subset of the plurality of selectable switching devices to receive the PWM control signal; and

, in response thereto

generating a PWM signal to adjust the envelope RF carrier output from the DPA.

18. The method of claim 17 further comprising receiving an input signal to be transmitted, for example an input amplitude sample that is split into an integer part and a fractional part.

19. The method of claim 18 further comprising inputting the fractional part to a PWM generator to produce the PWM control signal in response thereto.

20. The method of claim 18 wherein adjusting the envelope RF carrier output from the DPA comprises adding the integer part of the input signal to the generated PWM signal.

21. The method of claim 17 wherein generating the PWM signal to adjust the envelope RF carrier output from the DPA comprises adjusting a RF duty cycle of the PWM control signal.

22. A wireless communication unit comprising:

a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and

a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA;

wherein the PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.