OPEN LOOP COARSE TUNING FOR A PLL

• US 20110267146A1
• Filed: 04/30/2010
• Published: 11/03/2011
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dantoni, Francesco, Finocchiaro, Salvatore
• Granted Patent: US 8,130,047 B2
• Time in Patent Office: Days
• US Class Current: 331/2
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal

Abstract

In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Claims

1. An apparatus comprising:

an input circuit having a phase/frequency detector (PFD) and a charge pump, wherein the input circuit receives a reference clock signal and a feedback signal;

a low pass filter that is coupled to the input circuit;

a switch network that is coupled to the low pass filter;

a calibration generator that is coupled to the switch network;

a voltage controlled oscillator (VCO) bank having a plurality of VCOs, wherein the VCO bank is coupled to the switch network, and wherein the VCO bank provides an output clock signal;

a divider that is coupled to the VCO bank so as to receive the output clock signal;

a prescaler that is coupled to the divider;

a counting circuit that is coupled to the prescaler and the input circuit, wherein the counting circuit generates the feedback clock signal; and

calibration logic that is coupled to the prescaler, the divider, the switch network, and the VCO bank, wherein the calibration logic calibrates the VCO bank in a first mode of a plurality of modes for a target frequency, and wherein the calibration logic selects at least one of the VCOs having a tuning range that includes the target frequency during calibration in the first mode, and wherein the calibration logic trims the selected VCO to within a predetermined range of the target frequency, and wherein the calibration logic controls the switch network so as to decouple the low pass filter from the VCO bank and to coupled the calibration generator to the low pass filter and the VCO bank.

2. The apparatus of claim 1, wherein the apparatus further comprises a serial peripheral interface (SPI) that is coupled to the calibration logic, wherein the target frequency is adapted to be programmed through the SPI.

3. The apparatus of claim 2, wherein the divider and the prescaler are a variable divider and a variable prescaler that are each controlled by the calibration logic during calibration in the first mode.

4. The apparatus of claim 3, wherein the variable divider is adapted to divided by 1, 2, or 4, and wherein the variable prescaler is adapted to prescale by ⅘

or 8/9, and wherein the predetermined range is one least significant bit (LSB) above or below the target frequency.

5. The apparatus of claim 3, wherein the counting circuit further comprises first and second counters that measure the VCO tuning ranges during calibration in the first mode.

6. The apparatus of claim 5, wherein, in a second mode of the plurality of modes, the calibration logic measures and stores, for at least one of the VCOs, its tuning range.

7. The apparatus of claim 6, wherein the apparatus further comprises a buffer that is coupled between the VCO bank and the variable divider.

8. An apparatus comprising:

an in-phase/quadrature (IQ) modulator that receives a local oscillator clock signal; and

a local oscillator having;

an input circuit having a PFD and a charge pump, wherein the input circuit receives a reference clock signal and a feedback signal;

a low pass filter that is coupled to the input circuit;

a switch network that is coupled to the low pass filter;

a calibration generator that is coupled to the switch network;

a VCO bank having a plurality of VCOs, wherein the VCO bank is coupled to the switch network, and wherein the VCO bank provides the local oscillator clock signal;

a divider that is coupled to the VCO bank so as to receive the local oscillator clock signal;

a prescaler that is coupled to the divider;

a counting circuit that is coupled to the prescaler and the input circuit, wherein the counting circuit generates the feedback clock signal; and

calibration logic that is coupled to the prescaler, the divider, and the VCO bank, wherein the calibration logic calibrates the VCO bank in a first mode of a plurality of modes for a target frequency, and wherein the calibration logic selects at least one of the VCOs having a tuning range that includes the target frequency during calibration in the first mode, and wherein the calibration logic trims the selected VCO to within a predetermined range of the target frequency, and wherein the calibration logic controls the switch network so as to decouple the low pass filter from the VCO bank and to coupled the calibration generator to the low pass filter and the VCO bank.

9. The apparatus of claim 8, wherein the local oscillator further comprises an SPI that is coupled to the calibration logic, wherein the target frequency is adapted to be programmed through the SPI.

10. The apparatus of claim 9, wherein the divider and the prescaler are a variable divider and a variable prescaler that are each controlled by the calibration logic during calibration in the first mode.

11. The apparatus of claim 10, wherein the variable divider is adapted to divided by 1, 2, or 4, and wherein the variable prescaler is adapted to prescale by ⅘

or 8/9, and wherein the predetermined range is one least significant bit (LSB) above or below the target frequency.

12. The apparatus of claim 10, wherein the counting circuit further comprises first and second counters that measure the VCO tuning ranges during calibration in the first mode.

13. The apparatus of claim 12, wherein, in a second mode of the plurality of modes, the calibration logic measures and stores, for at least one of the VCOs, its tuning range.

14. The apparatus of claim 13, wherein the local oscillator further comprises a buffer that is coupled between the VCO bank and the variable divider.

15. The apparatus of claim 13, wherein the IQ modulator further comprises:

a first mixer;

a second mixer;

a phase adjust circuit that is coupled to the local oscillator, the first mixer, and the second mixer, wherein the phase adjust circuit provides the local oscillator clock signal to the first mixer, and wherein the phase adjust circuit provides a 90°

phase shifted local oscillator clock signal to the second mixer; and

an adder that is coupled to the first and second mixers.

16. An apparatus comprising:

a transmit processor;

a first digital-to-analog converter (DAC) that is coupled to the transmit processor;

a second DAC that is coupled to the transmit processor;

an IQ modulator that is coupled to the first and second DACs and that receives a local oscillator clock signal;

a local oscillator having;

an input circuit having a PFD and a charge pump, wherein the input circuit receives a reference clock signal and a feedback signal;

a low pass filter that is coupled to the input circuit;

a switch network that is coupled to the low pass filter;

a calibration generator that is coupled to the switch network;

a VCO bank having a plurality of VCOs, wherein the VCO bank is coupled to the switch network, and wherein the VCO bank provides the local oscillator clock signal;

a divider that is coupled to the VCO bank so as to receive the local oscillator clock signal;

a prescaler that is coupled to the divider;

a counting circuit that is coupled to the prescaler and the input circuit, wherein the counting circuit generates the feedback clock signal; and

calibration logic that is coupled to the prescaler, the divider, and the VCO bank, wherein the calibration logic calibrates the VCO bank in a first mode of a plurality of modes for a target frequency, and wherein the calibration logic selects at least one of the VCOs having a tuning range that includes the target frequency during calibration in the first mode, and wherein the calibration logic trims the selected VCO to within a predetermined range of the target frequency, and wherein the calibration logic controls the switch network so as to decouple the low pass filter from the VCO bank and to coupled the calibration generator to the low pass filter and the VCO bank;

a programmable gain amplifier that is coupled to the IQ modulator;

a power amplifier that is coupled to the programmable gain amplifier;

a radio frequency (RF) coupled that is coupled to the power amplifier; and

a feedback circuit that is coupled between the transmit processor and the RF coupler.

17. The apparatus of claim 16, wherein the local oscillator further comprises an SPI that is coupled to the calibration logic, wherein the target frequency is adapted to be programmed through the SPI, and wherein the divider and the prescaler are a variable divider and a variable prescaler that are each controlled by the calibration logic during calibration in the first mode.

18. The apparatus of claim 17, wherein the variable divider is adapted to divided by 1, 2, or 4, and wherein the variable prescaler is adapted to prescale by ⅘

or 8/9, and wherein the predetermined range is one LSB above or below the target frequency.

19. The apparatus of claim 17, wherein the counting circuit further comprises first and second counters that measure the VCO tuning ranges during calibration in the first mode, and wherein, in a second mode of the plurality of modes, the calibration logic measures and stores, for each VCO, its tuning range, and wherein the local oscillator further comprises a buffer that is coupled between the VCO bank and the variable divider.

20. The apparatus of claim 19, wherein the IQ modulator further comprises:

a first mixer that is coupled to the first DAC;

a second mixer that is coupled to the second DAC;

a phase adjust circuit that is coupled to the local oscillator, the first mixer, and the second mixer, wherein the phase adjust circuit provides the local oscillator clock signal to the first mixer, and wherein the phase adjust circuit provides a 90°

phase shifted local oscillator clock signal to the second mixer; and

an adder that is coupled to the first and second mixers.