DRAM-LIKE NVM MEMORY ARRAY AND SENSE AMPLIFIER DESIGN FOR HIGH TEMPERATURE AND HIGH ENDURANCE OPERATION

• US 20110267883A1
• Filed: 04/27/2011
• Published: 11/03/2011
• Est. Priority Date: 05/03/2010
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: HSU, FU-CHANG, LEE, PETER WUNG
• Granted Patent: US 8,559,232 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate

Abstract

A DRAM-like non-volatile memory array includes a cell array of non-volatile cell units with a DRAM-like cross-coupled latch-type sense amplifier. Each non-volatile cell unit has two non-volatile cell devices with respective bit lines and source lines running in parallel and laid out perpendicular to the word line associated with the non-volatile cell unit. The two non-volatile cell devices are programmed with erased and programmed threshold voltages as a pair for storing a single bit of binary data. The two bit lines of each non-volatile cell unit are coupled through a Y-decoder and a latch device to the two respective inputs of the latch-type sense amplifier which provides a large sensing margin for the cell array to operate properly even with a narrowed threshold voltage gap. Each non-volatile cell device may be a 2 T FLOTOX-based EEPROM cell, a 2 T flash cell, 11 T flash cell or a 1.5 T split-gate flash cell.

Claims

1. A DRAM-like non-volatile memory (NVM) array, comprising:

a matrix of a plurality of NVM cell units arranged in a plurality of rows and columns, each of said NVM cell unit including a first NVM cell device and a second NVM cell device as a pair with each NVM cell device having a drain node and a source node;

a plurality of word lines, each word line associated with a row of said NVM cell units;

a plurality of bit line pairs, each bit line pair associated with a column of said NVM cell units, and each bit line pair having a first bit line connected to the drain nodes of the first NVM cell devices in the associated column, and a second bit line connected to the drain nodes of the second NVM cell devices in the associated column, said bit line pairs being laid out perpendicular to said word lines;

a plurality of source line pairs, each source line pair associated with a column of said NVM cell units, and each source line pair having a first source line connected to the source nodes of the first NVM cell devices in the associated column, and a second source line connected to the source nodes of the second NVM cell devices in the associated column, said source line pairs being laid out perpendicular to said word lines;

a plurality of column decoders, each column decoder associated with a column of said NVM cell units; and

a plurality of cross-coupled latch-type sense amplifiers, each latch-type sense amplifier associated with a column of said NVM cell units, each latch-type sense amplifier having symmetric first and second inputs coupled to the first and second bit lines in the associated column through the associated column decoder;

wherein in each NMV cell unit, the first NVM cell device and the second NVM cell device each have a floating-gate storage cell, and the two floating-gate storage cells are programmed with respective erased and programmed threshold voltages as a pair to store only one bit of binary data.

2. The DRAM-like NVM array according to claim 1, wherein the first and second source lines of each column of said NVM cell units are coupled to a source voltage line through the associated column decoder.

3. The DRAM-like NVM array according to claim 1, wherein in each column of said NVM cell units, the first bit line and the first source line are coupled to a program control signal by a first program signal coupling device, and the second bit line and the second source line are coupled to the program control signal by a second program signal coupling device.

4. The DRAM-like NVM array according to claim 1, wherein each column decoder is a multi-level decoder for coupling the first and second bit lines to the first and second inputs of the sense amplifier in the associated column.

5. The DRAM-like NVM array according to claim 1, wherein each column decoder has two inputs respectively connected to the first and second bit lines of the associated column, and two outputs respectively coupled to two inputs of the associated sense amplifier.

6. The DRAM-like NVM array according to claim 5, wherein each column decoder further has a pair of input discharging devices for respectively coupling the two inputs of the associated column decoder to ground, and a pair of output discharging devices for respectively the two outputs of the associated column decoder to ground.

7. The DRAM-like NVM array according to claim 1, wherein each latch-type sense amplifier is coupled to the associated column decoder by a pair of latch devices controlled by a latch signal to respectively isolate the two inputs of each sense amplifier from the associated column decoder.

8. The DRAM-like NVM array according to claim 1, wherein each latch-type sense amplifier further comprises:

two cross-coupled PMOS devices having respective drains connected respectively to the first and second inputs of the corresponding sense amplifier, and respective sources connected to a common-source PMOS transistor; and

two cross-coupled NMOS devices having respective drains connected respectively to the first and second inputs of the corresponding sense amplifier, and respective sources connected to a common-source NMOS transistor.

9. The DRAM-like NVM array according to claim 1, further comprising a bit-read operation divided into three steps including discharging, charging and development for reading a selected NVM cell unit.

10. The DRAM-like NVM array according to claim 1, wherein each byte of said NVM cell units has eight first bit lines, eight second bit lines, eight first source lines, eight second source lines and a byte-gated bit line running in parallel.

11. The DRAM-like NVM array according to claim 1, wherein the first and second bit lines of each NVM cell unit are respectively coupled through respective pass-transistors to a shared high voltage bit latch in a page buffer.

12. The DRAM-like NVM array according to claim 1, wherein the first and second bit lines of each NVM cell unit are respectively coupled through respective pass-transistors to two respective high voltage bit latches in a page buffer.

13. The DRAM-like NVM array according to claim 1, further comprising a page-write operation having a first step of a page-erase operation followed by a second step of a page-program operation.

14. The DRAM-like NVM array according to claim 13, wherein a page is divided into an odd-half page and an even-half page in the second step of the page-program operation, and verification of the page-program operation is performed after both odd-half and even-off pages are programmed.

15. The DRAM-like NVM array according to claim 13, wherein a page is divided into an odd-half page and an even-half page in the second step of the page-program operation, and one of the odd-half and even-half pages is programmed and then immediately verified before the other of the odd-half and even-half pages is programmed and verified.

16. The DRAM-like NVM array according to claim 1, wherein each NVM cell device is a 2T FLOTOX-based EEPRM cell comprising:

a 1-poly NMOS select transistor having a drain connected to the drain node of the corresponding NVM cell device, and a gate connected to an associated word line; and

a 2-poly NMOS floating-gate transistor having a drain connected to a source of the 1-poly NMOS select transistor, a source connected to the source node of the corresponding NVM cell device, and a gate.

17. The DRAM-like NVM array according to claim 16, wherein each byte of said NVM cell units has eight first bit lines, eight second bit lines, eight first source lines, eight second source lines and a byte-gated bit line running in parallel.

18. The DRAM-like NVM array according to claim 16, wherein each byte of said NVM cell units comprises eight adjacent NVM cell units on a same row, a common gate connected to the gate of each 2-poly floating-gate transistor in the eight adjacent NVM cell units in the byte, and an NMOS common gate select transistor having a gate connected to the word line of the corresponding row and coupling the common gate to a byte-gated bit line.

19. The DRAM-like NVM array according to claim 18, wherein each column decoder has at least one decoder line, at least one NMOS select transistor with a gate connected to the decoder line for coupling the first bit line to the first input of the associated sense amplifier, at least one NMOS select transistor with a gate connected to the decoder line for coupling the second bit line to the second input of the associated sense amplifier.

20. The DRAM-like NVM array according to claim 19, wherein each of the first and second source lines of each column of said NVM cell units is coupled to a source voltage line through at least one NMOS select transistor with a gate connected to the decoder line.

21. The DRAM-like NVM array according to claim 20, wherein in each column of said NVM cell units, the first bit line and the first source line are coupled to a program control signal by a first NMOS program signal coupling device, and the second bit line and the second source line are coupled to the program control signal by a second NMOS program signal coupling device.

22. The DRAM-like NVM array according to claim 21, wherein each column decoder has two inputs respectively connected to the first and second bit lines of the associated column, and two outputs respectively coupled to two inputs of the associated sense amplifier.

23. The DRAM-like NVM array according to claim 22, wherein each column decoder further has a pair of NMOS discharging devices for respectively coupling the two inputs of the associated column decoder to ground, and another pair of NMOS discharging devices for respectively coupling the two outputs of the associated column decoder to ground.

24. The DRAM-like NVM array according to claim 23, wherein each latch-type sense amplifier is coupled to the associated column decoder by a pair of NMOS latch devices controlled by a latch signal to respectively isolate the two inputs of each sense amplifier from the associated column decoder.

25. The DRAM-like NVM array according to claim 24, wherein each latch-type sense amplifier further comprises:

two cross-coupled PMOS devices having respective drains connected respectively to the first and second inputs of the corresponding sense amplifier, and respective sources connected to a common-source PMOS transistor controlled by a first development signal; and

two cross-coupled NMOS devices having respective drains connected respectively to the first and second inputs of the corresponding sense amplifier, and respective sources connected to a common-source NMOS transistor controlled by a second development signal.

26. The DRAM-like NVM array according to claim 25, further comprising a bit-erase operation accomplished by the following voltage conditions for erasing a selected NVM cell unit:

applying a high voltage of approximately 16V to the byte-gated bit line of the associated column of the selected NVM cell unit;

applying a high voltage of approximately 16V to the gate of the NMOS common gate select transistor of the row corresponding to the selected NVM cell unit;

applying a voltage of approximately 0V to the remaining rows not corresponding to the selected NVM cell unit; and

applying a voltage of approximately 0V to the first and second bit lines of the associated column, the source voltage line, and the decoder line.

27. The DRAM-like NVM array according to claim 26, wherein each of the two 2-poly NMOS floating-gate transistors in the selected NVM cell unit has a threshold voltage increased to above 4.1V.

28. The DRAM-like NVM array according to claim 25, further comprising a bit-program operation accomplished by the following voltage conditions for programming a selected NVM cell unit:

applying a voltage of approximately 0V to the byte-gated bit line of the associated column of the selected NVM cell unit;

applying a high voltage of approximately 16V to the gate of the NMOS common gate select transistor of the row corresponding to the selected NVM cell unit;

applying a voltage of approximately 0V to the remaining rows not corresponding to the selected NVM cell unit;

applying a voltage of approximately 0V to source voltage line;

applying a voltage of approximately 7V greater than a threshold voltage of the NMOS program signal coupling devices to the program control signal; and

applying a power supply voltage VDD to the decoder line.

29. The DRAM-like NVM array according to claim 28, further applying a voltage of approximately 0V to both the bit line and the source line of the 2-poly NMOS floating-gate transistor in the selected NVM cell unit to be programmed with a decreased threshold voltage of a lower value, and applying a first voltage of approximately 16V and a second voltage of approximately 7V respectively to the bit line and the source line of the other 2-poly NMOS floating-gate transistor in the selected NVM cell unit desired to keep an unchanged threshold voltage.

30. The DRAM-like NVM array according to claim 29, wherein the decreased threshold voltage is below −

1.6V and the unchanged threshold voltage is above 4.1V.

31. The DRAM-like NVM array according to claim 25, further comprising a bit-read operation divided into three steps including discharging, charging and development for reading a selected NVM cell unit.

32. The DRAM-like NVM array according to claim 31, wherein the step of discharging is accomplished by applying a power supply voltage VDD to gates of the NMOS discharging devices in the associated column, the source voltage line, and the decoder line.

33. The DRAM-like NVM array according to claim 31, wherein the step of charging is accomplished by applying a voltage equal to or less than a voltage level of the first source line or the second source line in the selected NVM cell unit.

34. The DRAM-like NVM array according to claim 31, wherein the step of development is accomplished by grounding the latch signal to turn off the NMOS latch devices in the associated column, and using the first and second development signals to turn on the common-source PMOS transistor and the common-source NMOS transistor in the associated latch-type sense amplifier.

35. The DRAM-like NVM array according to claim 16, wherein the first and second bit lines of each NVM cell unit are respectively coupled through respective pass-transistors to a shared high voltage bit latch in a page buffer.

36. The DRAM-like NVM array according to claim 16, wherein the first and second bit lines of each NVM cell unit are respectively coupled through respective pass-transistors to two respective high voltage bit latches in a page buffer.

37. The DRAM-like NVM array according to claim 16, further comprising a page-write operation including a first step of a page-erase operation followed by a second step of a page-program operation.

38. The DRAM-like NVM array according to claim 37, wherein a page is divided into an odd-half page and an even-half page in the second step of the page-program operation, and verification of the program operation is performed after both odd-half and even-off pages are programmed.

39. The DRAM-like NVM array according to claim 37, wherein a page is divided into an odd-half page and an even-half page in the second step of the page-program operation, and one of the odd-half and even-half pages is programmed and then immediately verified before the other of the odd-half and even-half pages is programmed and verified.

40. The DRAM-like NVM array according to claim 1, wherein each NVM cell device is a 2T flash cell comprising:

a 2-poly floating-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, and a gate connected to an associated word line; and

a 1-poly select transistor having a drain connected to a source of the 2-poly float-gate transistor, a source connected to the source node of the corresponding NVM cell device, and a gate;

wherein the 2T flash cell is formed in a triple P-well within a deep N-well on top of a P-substrate.

41. The DRAM-like NVM array according to claim 1, wherein each NVM cell device is a 1T flash cell comprising:

a 2-poly floating-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, a gate connected to an associated word line, and a source connected to the source node of the corresponding NVM cell device;

wherein the 1T flash cell is formed in a triple P-well within a deep N-well on top of a P-substrate.

42. The DRAM-like NVM array according to claim 1, wherein each NVM cell device is a 1.5T split-gate flash cell comprising:

a 2-poly split-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, a gate connected to an associated word line, and a source connected to the source node of the corresponding NVM cell device;

wherein the 1.5T split-gate flash cell is formed on top of a P-substrate and comprises two 2-poly floating-gate transistors connected in series and physically squeezed into one transistor area.

43. The DRAM-like NVM array according to claim 1, wherein each two word lines are associated with a same row of said NVM cell units and each NVM cell device is 2T flash cell comprising:

a first 2-poly floating-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, and a gate connected to a first associated word line; and

a second 2-poly floating-gate transistor having a drain connected to a source of the first 2-poly float-gate transistor, a source connected to the source node of the corresponding NVM cell device, and a gate connected to a second associated word line;

wherein the 2T flash cell is formed in a triple P-well within a deep N-well on top of a P-substrate.

44. A non-volatile memory NVM cell unit, comprising:

a first NVM cell device having a drain node connected to a first bit line, a source node connected to a first source line and a gate coupled to a word line associated with the NVM cell unit; and

a second NVM cell device having a drain node connected to a second bit line, a source node connected to a second source line and a gate coupled to the associated word line;

wherein the two bit lines and the two source lines are running in parallel and laid out perpendicular to the associated word line, the first NVM cell device and the second NVM cell device each have a floating-gate storage cell, and the two storage floating-gate cells are programmed with respective erased and programmed threshold voltages as a pair to store only one bit of binary data.

45. The non-volatile memory NVM cell unit according to claim 44, wherein each of the first and second NVM cell devices is a 2T FLOTOX-based EEPRM cell comprising:

a 1-poly NMOS select transistor having a drain connected to the drain node of the corresponding NVM cell device, and a gate connected to the associated word line; and

a 2-poly NMOS floating-gate transistor having a drain connected to a source of the 1-poly NMOS select transistor, a source connected to the source node of the corresponding NVM cell device, and a gate coupled to the associated word line.

46. The non-volatile memory NVM cell unit according to claim 44, wherein each of the first and second NVM cell devices is a 2T flash cell comprising:

a 2-poly floating-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, and a gate connected to the associated word line; and

a 1-poly select transistor having a drain connected to a source of the 2-poly float-gate transistor, a source connected to the source node of the corresponding NVM cell device, and a gate connected to a select line associated with the NVM cell unit;

wherein the 2T flash cell is formed in a triple P-well within a deep N-well on top of a P-substrate.

47. The non-volatile memory NVM cell unit according to claim 44, wherein each of the first and second NVM cell devices is a 1T flash cell comprising:

a 2-poly floating-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, a gate connected to the associated word line, and a source connected to the source node of the corresponding NVM cell device;

wherein the 1T flash cell is formed in a triple P-well within a deep N-well on top of a P-substrate.

48. The non-volatile memory NVM cell unit according to claim 44, wherein each of the first and second NVM cell devices is a 1.5T split-gate flash cell comprising:

a 2-poly split-gate transistor having a drain connected to the drain node of the corresponding NVM cell device, a gate connected to the associated word line, and a source connected to the source node of the corresponding NVM cell device;

wherein the 1.5T split-gate flash cell is formed on top of a P-substrate and comprises two 2-poly floating-gate transistors connected in series and physically squeezed into one transistor area.