SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20110267892A1
• Filed: 04/28/2011
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Hyung Seok
• Granted Patent: US 8,526,239 B2
• Time in Patent Office: Days
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.

Claims

1. A semiconductor memory device, comprising:

a memory string coupled to a bit line;

a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation; and

a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.

2. The semiconductor memory device of claim 1, wherein the sensing control circuit controls the level of the sensing current in proportion to the threshold voltage level of the selected memory cell.

3. The semiconductor memory device of claim 1, wherein:

the level of the sensing current for the erase verification operation is set to a first level,

the level of the sensing current for a program verification operation of a first program level is set to a second level which is higher than the first level,

the level of the sensing current for a program verification operation of a second program level is set to a third level which is higher than the second level, and

the level of the sensing current for a program verification operation of a third program level is set to a fourth level which is higher than the third level.

4. The semiconductor memory device of claim 1, wherein the level of the sensing current of the bit line is higher than the level of the sensing current of the bit line in the erase verification operation.

5. The semiconductor memory device of claim 1, wherein the sensing control circuit comprises:

a sensing voltage generator configured to generate a first voltage when the bit line is precharged and to generate a second voltage, which is lower than the first voltage, when the sensing current is supplied from the bit line to the page buffer; and

a sensing circuit configured to control a connection of the bit line and the page buffer according to the first voltage or the second voltage.

6. The semiconductor memory device of claim 5, wherein the sensing voltage generator generates the second voltage, having a higher level when data of the selected memory cell is verified in the program verification operation than when the data of the selected memory cell is verified in the erase verification operation.

7. The semiconductor memory device of claim 6, wherein:

the sensing voltage generator generates the second voltage having a first sensing level in the erase verification operation,

the sensing voltage generator generates the second voltage having a second sensing level, which is higher than the first sensing level, in a program verification operation of a first program level,

the sensing voltage generator generates the second voltage having a third sensing level, which is higher than the second sensing level, in a program verification operation of a second program level, and

the sensing voltage generator generates the second voltage having a fourth sensing level, which is higher than the third sensing level, in a program verification operation of a third program level.

8. The semiconductor memory device of claim 5, wherein the sensing voltage generator generates the first voltage, having a higher level when data of the selected memory cell is verified in the program verification operation than when the data of the selected memory cell is verified in the erase verification operation.

9. The semiconductor memory device of claim 8, wherein:

the sensing voltage generator generates the first voltage having a first precharge level in the erase verification operation,

the sensing voltage generator generates the first voltage having a second precharge level, which is higher than the first precharge level, in a program verification operation of a first program level,

the sensing voltage generator generates the first voltage having a third precharge level, which is higher than the second precharge level, in a program verification operation of a second program level, and

the sensing voltage generator generates the first voltage having a fourth precharge level, which is higher than the third precharge level, in a program verification operation of a third program level.

10. The semiconductor memory device of claim 5, wherein an evaluation time is decreased by the sensing voltage generator, which elapses from the time the first voltage is supplied until the second voltage is supplied, when the program verification operation is performed than when the erase verification operation is performed.

11. The semiconductor memory device of claim 10, wherein:

the evaluation time is set to a first value in the erase verification operation,

the evaluation time is set to a second value, which is less than the first value, in a program verification operation of a first program level,

the evaluation time is set to a third value, which is less than the second value, in a program verification operation of a second program level, and

the evaluation time is set to a fourth value, which is less than the third value, in a program verification operation of a third program level.

12. A method of operating a semiconductor memory device, the method comprising:

performing an erase operation on a memory string coupled to a bit line;

after the erase operation, setting a level of a sensing current to a first level and performing an erase verification operation for verifying a stored data in a selected memory cell of the memory string;

performing a program operation on the selected memory cell; and

after the program operation, setting a level of the sensing current for a program verification operation to one of several program levels which is higher than the first level and performing the program verification operation for verifying the stored data in the memory cell.

13. The method of claim 12, wherein setting a level of the sensing current for the program verification operation comprises:

setting the level of the sensing current to a second level in a program verification operartion of a first program level,

setting the level of the sensing current to a third level which is higher than the second level in a program verification operartion of a second program level, and setting the level of the sensing current to a fourth level which is higher than the third level in a program verification operartion of a third program level.

14. A method of operating a semiconductor memory device, the method comprising:

performing an erase operation on a memory string coupled to a bit line;

precharging the bit line to a first bit line voltage after the erase operation;

performing an erase verification operation by sensing a change of a voltage of the bit line;

performing a program operation on a selected memory cell;

precharging the bit line to one of several bit line voltages, which is higher than the first bit line voltage, after the program operation; and

performing a program verification operation by sensing a change of a voltage of the bit line.

15. The method of claim 14, wherein precharing the bit line after the program operation comprises:

precharging the bit line to a second bit line voltage, which is higher than the first bit line voltage in a program verification operation of a first program level,

precharging the bit line to a third bit line voltage, which is higher than the second bit line voltage in a program verification operation of a second program level, and

precharging the bit line to a fourth bit line voltage, which is higher than the third bit line voltage in a program verification operation of a third program level.

16. A method of operating a semiconductor memory device, the method comprising:

performing an erase operation on a memory string coupled to a bit line;

precharging the bit line after performing the erase operation;

performing an erase verification operation by sensing a change of a voltage of the bit line after an evaluation time having a first value;

performing a program operation on a selected memory cell;

precharging the bit line after performing the program operation; and

performing a program verification operation by sensing a change of a voltage of the bit line after an evaluation time having one value of several values, which is less than the first value.

17. The method of claim 16, wherein the evaluation time is a time for which data stored in the selected memory cell is verified, and is a time elapsing from a time when a first voltage for precharging the bit line is supplied until a second voltage for sensing the change of the voltage of the bit line is supplied.

18. The method of claim 16, wherein:

the evaluation time is set to a second value which is less than the first value in a program verification operation of a first program level,

the evaluation time is set to a third value which is less than the second value in a program verification operation of a second program level, and

the evaluation time is set to a fourth value which is less than the third value in a program verification operation of a third program level.