SEMICONDUCTOR MEMORY DEVICE HAVING DRAM CELL MODE AND NON-VOLATILE MEMORY CELL MODE AND OPERATION METHOD THEREOF

• US 20110267903A1
• Filed: 07/14/2011
• Published: 11/03/2011
• Est. Priority Date: 08/23/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: HUO, Zong-Liang, YEO, In-Seok
• Application Number:
  US13/182,995
• Publication Number:
  US 20110267903A1
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

Claims

1-19. -19. (canceled)

20. A method of operating a semiconductor memory device having memory cells arranged in an array, each of the memory cells including a semiconductor substrate, a floating body disposed on the semiconductor substrate, a gate electrode insulated from the floating body, a source and a drain disposed in the semiconductor substrate at both sides of the gate electrode, and a charge storage region interposed between the floating body and the gate electrode, the method comprising:

selecting at least one cell of memory cells;

determining whether the selected sell is to operate in a DRAM cell mode or a non-volatile memory cell mode; and

operating the selected cell in the DRAM cell mode or the non-volatile memory cell mode, after determining an operational mode.