THIN FILM TRANSISTORS HAVING MULTIPLE DOPED SILICON LAYERS

• US 20110269274A1
• Filed: 10/28/2010
• Published: 11/03/2011
• Est. Priority Date: 11/03/2009
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kenji, Omori, Furuta, Gaku, Choi, Soo Young
• Granted Patent: US 8,299,466 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.

Claims

1. A thin film transistor fabrication method, comprising:

depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;

depositing two or more doped silicon layers over the amorphous silicon layer, each doped silicon layer having at least one characteristic that is different than the other doped silicon layers;

depositing a metal layer over the two or more doped silicon layers;

patterning the metal layer to form a source electrode and a drain electrode;

patterning the two or more doped silicon layers to expose the amorphous silicon layer; and

depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.

2. The method of claim 1, wherein depositing the two or more doped silicon layers comprises:

depositing a first doped silicon layer on the amorphous silicon layer under first deposition conditions; and

depositing a second doped silicon layer on the first doped silicon layer under second deposition conditions different than the first deposition conditions.

3. The method of claim 2, wherein the first doped silicon layer has a first resistivity and the second doped silicon layer has a second resistivity lower than the first resistivity.

4. The method of claim 2, wherein the deposition rate for the first doped silicon layer is greater than the deposition rate for the second doped silicon layer.

5. The method of claim 2, wherein the first doped silicon layer comprises amorphous silicon and the second doped silicon layer comprises microcrystalline silicon.

6. The method of claim 2, wherein both the first doped silicon layer and the second doped silicon layer comprise amorphous silicon.

7. The method of claim 2, wherein:

the first deposition conditions comprise a deposition rate of between about 800 Angstroms per minute and about 4000 Angstroms per minute, a deposition time of up to about 30 seconds to produce a first doped silicon layer having a resistivity of between about 70 Ω

cm to about 3000 Ω

cm; and

the second deposition conditions comprise a deposition rate of between about 50 Angstroms per minute and about 800 Angstroms per minute for a deposition time of between about 15 seconds to about 3000 seconds to produce the second doped silicon layer having a resistivity of between about 10 Ω

cm to about 70 Ω

cm.

8. The method of claim 2, wherein:

the first deposition conditions comprise a deposition rate of between about 1800 Angstroms per minute and about 2200 Angstroms per minute, a deposition time of between about 5 seconds and about 10 seconds to produce a first doped silicon layer having a resistivity of between about 110 Ω

cm to about 120 Ω

cm; and

the second deposition conditions comprise a deposition rate of between about 280 Angstroms per minute and about 320 Angstroms per minute for a deposition time of between about 10 seconds to about 18 seconds to produce the second doped silicon layer having a resistivity of between about 30 Ω

cm to about 40 Ω

cm.

9. The method of claim 2, wherein the second deposition comprises introducing silane gas at a flow rate of between about 5000 sccm and about 20000 sccm, introducing hydrogen gas at a flow rate of up to about 200000 sccm, introducing 0.5 percent PH₃ in H₂ at a flow rate of between about 1000 sccm and about 200000 sccm, applying an RF power to a showerhead of between about 500 W and about 15000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils.

10. The method of claim 2, wherein the second deposition comprises introducing silane gas at a flow rate of between about 5000 sccm and about 50000 sccm, introducing hydrogen gas at a flow rate of up to about 150000 sccm, introducing 0.5 percent PH₃ in H₂ at a flow rate of between about 1000 sccm and about 150000 sccm, applying an RF power to a showerhead of between about 10000 W and about 40000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils.

11. A thin film transistor fabrication method, comprising:

depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;

depositing a first doped silicon layer having a first resistivity on the amorphous silicon layer at a first deposition rate;

depositing a second doped silicon layer having a second resistivity less than the first resistivity on the first doped silicon layer, the second doped silicon layer deposited at a second deposition rate less than the first deposition rate;

depositing a metal layer over the second doped silicon layer;

patterning the metal layer to form a source electrode and a drain electrode;

patterning the first doped silicon layer and the second doped silicon layer to expose the amorphous silicon layer; and

depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.

12. The method of claim 11, further comprising depositing a third doped silicon layer having a third resistivity less than the second resistivity on the second doped silicon layer, the third doped silicon layer deposited at a third deposition rate that is less than the second deposition rate.

13. The method of claim 11, wherein the first doped silicon layer comprises amorphous silicon and the second doped silicon layer comprises microcrystalline silicon.

14. The method of claim 11, wherein:

the first doped silicon layer is deposited under first deposition conditions that comprise a deposition rate of between about 800 Angstroms per minute and about 4000 Angstroms per minute, a deposition time of up to about 30 seconds to produce a first doped silicon layer having a resistivity of between about 70 Ω

cm to about 300 Ω

cm; and

the second doped silicon layer is deposited under second deposition conditions that comprise a deposition rate of between about 50 Angstroms per minute and about 800 Angstroms per minute for a deposition time of between about 15 seconds to about 300 seconds to produce the second doped silicon layer having a resistivity of between about 10 Ω

cm to about 70 Ω

cm.

15. The method of claim 11, wherein:

the first doped silicon layer is deposited under first deposition conditions that comprise a deposition rate of between about 1800 Angstroms per minute and about 2200 Angstroms per minute, a deposition time of between about 5 seconds and about 10 seconds to produce a first doped silicon layer having a resistivity of between about 110 Ω

cm to about 120 Ω

cm; and

the second doped silicon layer is deposited under second deposition conditions that comprise a deposition rate of between about 280 Angstroms per minute and about 320 Angstroms per minute for a deposition time of between about 10 seconds to about 18 seconds to produce the second doped silicon layer having a resistivity of between about 30 Ω

cm to about 40 Ω

cm.

16. The method of claim 11, wherein the second doped silicon layer is deposited under deposition conditions that comprise introducing silane gas at a flow rate of between about 5000 sccm and about 20000 sccm, introducing hydrogen gas at a flow rate of up to about 200000 sccm, introducing 0.5 percent PH₃ in H₂ at a flow rate of between about 1000 sccm and about 200000 sccm, applying an RF power to a showerhead of between about 500 W and about 15000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils.

17. The method of claim 11, wherein the second doped silicon layer is deposited under deposition conditions that comprise introducing silane gas at a flow rate of between about 5000 sccm and about 50000 sccm, introducing hydrogen gas at a flow rate of up to about 150000 sccm, introducing 0.5 percent PH₃ in H₂ at a flow rate of between about 1000 sccm and about 150000 sccm, applying an RF power to a showerhead of between about 10000 W and about 40000 W, maintaining a chamber pressure of between about 1 Torr and about 5 Torr and a spacing between the showerhead and the substrate of between about 400 mils and about 1200 mils.

18. A thin film transistor fabrication method, comprising:

depositing an amorphous silicon layer over a substrate having a gate electrode and a gate dielectric layer formed thereon;

depositing a doped silicon layer on the amorphous silicon layer, the doped silicon layer having a resistivity that decreases from a first surface in contact with the amorphous silicon layer to a second surface opposite the first surface;

depositing a metal layer on the second surface of the doped silicon layer;

patterning the metal layer to form a source electrode and a drain electrode;

patterning the doped silicon layer to expose the amorphous silicon layer; and

depositing a passivation layer over the source electrode, the drain electrode and the exposed amorphous silicon layer.

19. The method of claim 18, wherein the doped silicon layer comprises amorphous silicon.

20. The method of claim 18, wherein the doped silicon layer comprises microcrystalline silicon.