High Voltage Transistor with Improved Driving Current

• US 20110269283A1
• Filed: 07/11/2011
• Published: 11/03/2011
• Est. Priority Date: 10/19/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, You-Kuo, Lin, Jui-Wen, Chen, Fu-Hsin, Tien, William Wei-Yuan
• Granted Patent: US 8,268,691 B2
• Time in Patent Office: Days
• US Class Current: 438/286
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers.

The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region;

forming a first doped region within the active region;

forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region;

forming at least one dielectric layer over sidewalls of the gate electrode;

forming a pair of spacers on the dielectric layer; and

forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers.

2. The method of claim 1, wherein forming at least one dielectric layer over sidewalls of the gate electrode further comprises blanket depositing a dielectric over the gate electrode and the substrate.

3. The method of claim 1, wherein blanket depositing a dielectric further comprises depositing a material one selected from the group consisting essentially of oxygen-containing dielectric, nitrogen containing dielectric, silicon dioxide, silicon nitride, and combinations thereof.

4. The method of claim 3, wherein blanket depositing a dielectric further comprises depositing a first dielectric material and depositing a second dielectric material over the first dielectric material.

5. The method of claim 4, wherein the first and second dielectric materials comprise the same dielectric material.

6. The method of claim 4, wherein the first and second dielectric materials comprise different dielectric materials.

7. The method of claim 6, wherein the first and second dielectric materials independently comprise a material one selected from the group consisting essentially of oxygen-containing dielectric, nitrogen containing dielectric, silicon dioxide, silicon nitride, and combinations thereof.

8. The method of claim 1, wherein forming a pair of spacers on the dielectric layer further comprises:

blanket depositing a spacer dielectric layer over the dielectric layer; and

anisotropically etching the spacer dielectric layer to remove horizontal portions, the spacer dielectric layer forming spacer regions on opposing sidewalls of the gate electrode.

9. The method of claim 8 wherein during the anisotropic etch of the spacer dielectric layer, the dielectric layer acts as an etch stop layer.

10. A method for forming an HVMOS transistor, comprising:

forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region;

forming a first doped region within the active region;

driving the first doped region into the active region to define a deep drain region;

forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region, the gate electrode having opposing sidewalls;

forming at least one dielectric layer over the sidewalls of the gate electrode;

forming a pair of spacers on the dielectric layer adjacent the sidewalls of the gate electrode;

forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers, the first and second doped regions forming a double diffused drain region for the HVMOS transistor; and

forming a source region in a portion of the active region spaced from the first doped region and opposite the gate electrode from the first doped region.

11. The method of claim 10, wherein the isolation regions are formed by LOCOS isolation.

12. The method of claim 10, wherein the isolation regions are formed by shallow trench isolation.

13. The method of claim 10, wherein driving the first doped region further comprises performing a thermal drive, the first doped region forming a graded concentration doped region.

14. The method of claim 10, wherein forming at least one dielectric layer over sidewalls of the gate electrode further comprises blanket depositing a dielectric over the gate electrode and the substrate.

15. The method of claim 14, wherein blanket depositing a dielectric further comprises depositing a material one selected from the group consisting essentially of oxygen-containing dielectric, nitrogen containing dielectric, silicon dioxide, silicon nitride, and combinations thereof.

16. The method of claim 15, wherein blanket depositing a dielectric further comprises depositing a first dielectric material and depositing a second dielectric material over the first dielectric material.

17. The method of claim 10, wherein forming a pair of spacers on the dielectric layer further comprises:

blanket depositing a spacer dielectric layer over the dielectric layer; and

anisotropically etching the spacer dielectric layer to remove horizontal portions, the spacer dielectric layer forming spacer regions on opposing sidewalls of the gate electrode, wherein during the anisotropic etch of the spacer dielectric layer, the dielectric layer acts as an etch stop layer.

18. The method of claim 10, further comprising positioning a gate-side boundary of the second doped region from a closest edge of the one of the spacers by more than about 0.2 μ

m.

19. The method of claim 10, further comprising positioning an isolation region-side boundary of the second doped region from a closest edge of the isolation region.

20. The method of claim 10, wherein a gate-side boundary of the second doped region is separated from a closest edge of the spacer by a first distance, and wherein an isolation region-side boundary of the second doped region is separated from a closest edge of the isolation region by a second distance, the second distance being less than the first distance.