HERMETIC WAFER-TO-WAFER BONDING WITH ELECTRICAL INTERCONNECTION

• US 20110270341A1
• Filed: 04/28/2011
• Published: 11/03/2011
• Est. Priority Date: 04/28/2010
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Smith, Jonathan R., Ruben, David A., Mattes, Michael F.
• Granted Patent: US 8,433,402 B2
• Time in Patent Office: Days
• US Class Current: 607/9
• CPC Class Codes: A61B 5/00 Measuring for diagnostic purposes radiation diagnosis A61B6/00; diagnosis by ultrasonic, sonic or infrasonic waves A61B8/00; Identification of persons
• CPC Class Codes: A61B 5/318 Heart-related electrical modalities, e.g. electrocardiography [ECG]
• CPC Class Codes: A61N 1/375 Constructional arrangements, e.g. casings
• CPC Class Codes: A61N 1/37512 Pacemakers
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/08058 being non uniform along the bonding area
• CPC Class Codes: H01L 2224/0807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08147 the bonding area connecting to a bonding area disposed in a recess of the surface of the body
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 : by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/13007 : Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 : in side view
• CPC Class Codes: H01L 2224/13021 : the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16111 : the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80092 : Atmospheric pressure
• CPC Class Codes: H01L 2224/80097 : Heating
• CPC Class Codes: H01L 2224/80213 : using a reflow oven
• CPC Class Codes: H01L 2224/80345 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/80815 : Reflow soldering
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80906 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83194 : Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9205 : Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
• CPC Class Codes: H01L 2224/9212 : Sequential connecting processes
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/564 : Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An implantable medical device (IMD) is disclosed. The IMD includes a first substrate having a front side and a backside. A first via is formed in the front side, the via extending from a bottom point in the front side to a first height located at a surface of the front side. A first conductive pad is formed in the first via, the first conductive pad having an exposed top surface lower than first height. A second substrate is coupled to the first substrate, the second substrate having a second via formed in the front side, the via extending from a bottom point in the front side to a second height located at a surface of the front side. A second conductive pad is formed in the second via, the second conductive pad having an exposed top surface lower than second height. The coupled substrates are heated until a portion of one or both conductive pads reflow, dewet, agglomerate, and merge to form an interconnect, hermetic seal, or both depending on the requirements of the device.

Claims

1. A method for forming an integrated circuit for an implantable medical device comprising:

forming a first via in a first side of a first substrate;

forming a first conductive pad in the first via, wherein an exposed top surface of the first conductive pad is lower than a top surface of the first via;

forming a second via in a first side of a second substrate;

forming a second conductive pad in the second via, wherein an exposed top surface of the second conductive pad is lower than a top surface of the second via; and

reflowing the first and second conductive pads to form a single reflowed interconnect that completely fills a gap between the first and second vias.

2. The method of claim 1 further comprising:

forming a hermetic seal between the first and second substrates in response to filling the gap.

3. The method of claim 1 further comprising a conductive pad by:

forming a first conductive material on a thermal oxide material; and

forming a second conductive material over the first conductive material.

4. The method of claim 3 further comprising:

forming a third conductive material over the second conductive material.

5. The method of claim 1 wherein the first conductive material consisting of titanium, the second conductive material consisting of gold (Au), and the third conductive material consisting of gold tin (AuSn).

6. The method of claim 1 wherein the first conductive material consisting of titanium, the second conductive material consisting of platinum (Pt), and the third conductive material consisting of AuSn.

7. The method of claim 1 wherein the first conductive material consisting of Ti, the second conductive material consisting of Au, and the third conductive material consisting of AuSn.

8. The method of claim 1 wherein the first conductive material consisting of Cr, the second conductive material consisting of Au, and the third conductive material consisting of AuSn.

9. The method of claim 1 wherein the first conductive pad and the second conductive pad consisting essentially of AuSn.

10. The method of claim 1 wherein the Au is present in an amount of about 80 weight percent and Sn is present in an amount of 20 weight percent of the AuSn.

11. The method of claim 1 wherein the Au is present in an amount of about 78 weight percent and Sn is present in an amount of 22 weight percent of the AuSn.

12. The method of claim 1 wherein one of the first conductive pad and the second conductive pad comprising of palladium, copper, nickel, rhodium, tin, platinum, or gold.

13. The method of claim 1 wherein the implantable medical device being an implantable leadless pacemaker.

14. The method of claim 1 wherein the implantable medical device being an implantable sensor.

15. The method of claim 1 wherein the implantable medical device is an implantable communication device.

16. The method of claim 1 wherein the implantable medical device is an implantable relay device.

17. The method of claim 1 wherein the implantable medical device is a medical electrical lead with at least one integrated circuit disposed in a lead body.

18. The method of claim 1 wherein the implantable medical device is a medical electrical lead with at least one integrated circuit disposed in a smart lead.

19. An integrated circuit for an implantable medical device comprising:

means for forming a first via in a first side of a first substrate;

means for forming a first conductive pad in the first via, wherein an exposed top surface of the first conductive pad is lower than a top surface of the first via;

means for forming a second via in a first side of a second substrate;

means for forming a second conductive pad in the second via, wherein an exposed top surface of the second conductive pad is lower than a top surface of the second via; and

means for heating until at least a portion of first and second conductive pads reflow and form an interconnect that completely fills a gap between the first and second vias.

20. A method comprising:

forming a first wafer with a frontside and a backside;

forming a second wafer with a frontside and a backside;

coupling the frontside of the first wafer to the frontside of the second wafer; and

polishing the frontside of either the first wafer or the second wafer such that only nonconductive material is contacted by a polishing device.

21. The method of claim 20 further comprising:

planarizing one of the first and second wafers without use of redundant electrical connections.

22. The method of claim 21 wherein the redundant electrical connections are nonelectrically working connections.

24. The integrated circuit of claim 21 wherein the medical component being one of a smart lead, a switch, and a sensor.

23. An integrated circuit for an implantable medical component comprising:

means for forming a first via in a first side of a first substrate;

means for forming a first conductive pad in the first via, wherein an exposed top surface of the first conductive pad is lower than a top surface of the first via;

means for forming a second via in a first side of a second substrate;

means for forming a second conductive pad in the second via, wherein an exposed top surface of the second conductive pad is lower than a top surface of the second via; and

means for heating until at least a portion of first and second conductive pads reflow and form an interconnect that completely fills a gap between the first and second vias.

35. The device of claim 23 wherein the Au is present in an amount of about 79 weight percent and Sn is present in an amount of 21 weight percent of the AuSn.

36. The device of claim 23 wherein the Au is present in an amount of about 78 weight percent and Sn is present in an amount of 22 weight percent of the AuSn

25. An implantable medical device comprising:

a first substrate having a front side and a backside;

a first via formed in the front side, the via extending from a bottom point in the front side to a first height located at a surface of the front side;

a first conductive pad formed in the first via, the first conductive pad having an exposed top surface lower than first height;

a second substrate coupled to the first substrate, the second substrate having a second via formed in the front side, the via extending from a bottom point in the front side to a second height located at a surface of the front side;

a second conductive pad formed in the second via, the second conductive pad having an exposed top surface lower than second height; and

means for reflowing one of the first and second conductive pads to form a single reflowed interconnect.

26. The device of claim 25 further comprising:

a first conductive material coupled to the first conductive pad and to a thermal oxide material;

a second conductive material coupled to the first conductive material; and

a third conductive material coupled to the second conductive material.

27. The device of claim 25 wherein the first conductive material consisting of titanium, the second conductive material consisting of Au, and the third conductive material consisting of chromium AuSn

28. The device of claim 25 wherein the first conductive material consisting of titanium, the second conductive material consisting of platinum (Pt), and the third conductive material consisting of AuSn.

29. The device of claim 25 wherein the first conductive material consisting of Ti, the second conductive material consisting of Au, and the third conductive material consisting of AuSn.

30. The device of claim 25 wherein the first conductive material consisting of Cr, the second conductive material consisting of Au, and the third conductive material consisting of AuSn.

31. The device of claim 25 further comprising:

a fourth conductive material disposed over the third conductive material.

32. The device of claim 31 wherein the first conductive material consisting of Ti, the second conductive material consisting of Ni, and the third conductive material consisting of Ti, and the fourth conductive material comprising AuSn.

33. The device of claim 25 wherein the first conductive pad and the second conductive pad consisting essentially of AuSn.

34. The device of claim 25 wherein the Au is present in an amount of about 80 weight percent and tin (Sn) is present in an amount of 20 weight percent of the AuSn.

37. The device of claim 25 wherein one of the first conductive pad and the second conductive pad consisting essentially of palladium, copper, nickel, rhodium, or tin.

38. The device of claim 25 is an implantable leadless pacemaker.

39. The device of claim 25 is an implantable sensor.

40. The device of claim 25 medical electrical lead with at least one integrated circuit disposed in a lead body.

41. The device of claim 25 wherein the first substrate being one of silicon and glass, glass to glass, glass to silicon, silicon to silicon, silicon to sapphire, sapphire to sapphire, and glass to sapphire.