SYSTEM AND METHOD FOR ALLOCATING AND USING SPARE BLOCKS IN A FLASH MEMORY

• US 20110271043A1
• Filed: 04/28/2011
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: SEGAL, Avigdor, Maly, Igal
• Granted Patent: US 9,021,177 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool.

Claims

1. A method of operating a Flash memory array comprising:

allocating a first portion of spare blocks in the Flash memory as a single level cell (SLC) spare block pool, and a second portion of spare blocks in the Flash memory as a multi-level cell (MLC) spare block pool;

replacing bad SLC blocks in the Flash memory with spare blocks from the SLC spare block pool; and

if the number of spare blocks in the SLC spare block pool is less than a minimum SLC spare pool threshold, then re-allocating spare blocks from the MLC spare block pool to the SLC spare block pool.

2. The method of claim 1, further comprising:

re-allocating MLC blocks reaching a maximum MLC bearable cycle count to the SLC spare block pool.

3. The method of claim 2, wherein the maximum MLC bearable cycle count comprises a predetermined number of P/E cycles.

4. The method of claim 1, further comprising:

declaring an end of life of the Flash memory array when the number of blocks in the MLC spare block pool is less than a minimum MLC spare pool threshold.

5. The method of claim 1, wherein the minimum SLC spare pool threshold comprises a minimum number of spare blocks required for smooth operation.

6. A Flash memory device comprising:

a plurality of Flash memory blocks; and

a controller to;

allocate a first portion of spare blocks in the Flash memory as a single level cell (SLC) spare block pool, and a second portion of spare blocks in the Flash memory as a multi-level cell (MLC) spare block pool;

replace bad SLC blocks in the Flash memory with spare blocks from the SLC spare block pool; and

if the number of spare blocks in the SLC spare block pool is less than a minimum SLC spare pool threshold, then re-allocate spare blocks from the MLC spare block pool to the SLC spare block pool.

7. The device of claim 6, wherein the controller is further configured to:

re-allocate MLC blocks reaching a maximum MLC bearable cycle count to the SLC spare block pool.

8. The device of claim 7, wherein the maximum MLC bearable cycle count is a predetermined number of P/E cycles.

9. The device of claim 6, wherein the controller is further configured to:

declare an end of life of the Flash memory array when the number of blocks in the MLC spare block pool is less than a minimum MLC spare pool threshold.

10. The device of claim 6, wherein the minimum SLC spare pool threshold comprises a minimum number of spare blocks required for smooth operation.

11. A method of operating a non-volatile memory array comprising:

allocating N number of portions of spare blocks in the non-volatile memory as N number of multi-level cell (MLCx(N)) spare block pools;

exchanging bad MLCx(j) blocks in the non-volatile memory with spare blocks from the MLCx(j) spare block pool; and

if the number of spare blocks in an MLCx(j) spare block pool is less than a minimum MLCx(j) spare pool threshold, then transferring spare blocks from the MLCx(j+1) spare block pool to the MLCx(j) spare block pool.

12. The method of claim 11, wherein an MLCx1 block comprises an SLC spare block.

13. The method of claim 11, wherein the non-volatile memory array comprises a Flash memory array.

14. The method of claim 11, wherein N is greater or equal to three.

15. The method of claim 11, further comprising:

transferring MLCx(j+1) blocks reaching a maximum MLCx(j+1) bearable cycle count to the MLCx(j) spare block pool.

16. The method of claim 11, further comprising:

declaring an end of life of the non-volatile memory array when the number of blocks in the MLCxN spare block pool is less than a minimum MLCxN spare pool threshold.