Optimizing Task Management

• US 20110271076A1
• Filed: 04/28/2010
• Published: 11/03/2011
• Est. Priority Date: 04/28/2010
• Status: Active Grant

• Current Assignee: Wind River Systems Incorporated (Aptiv PLC)
• Original Assignee: Wind River Systems Incorporated (Aptiv PLC)
• Inventors: Li, Stephen, Koning, Maarten
• Granted Patent: US 9,811,385 B2
• Time in Patent Office: Days
• US Class Current: 712/20
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206

Abstract

An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to one of the single-core processing mode and the multi-core processing mode as a function of the number of tasks.

Claims

1. An electronic device, comprising:

a processing component configurable for one of a single-core processing mode and a multi-core processing mode; and

a task manager determining a number of tasks running on the electronic device,

wherein the processor is configured to one of the single-core processing mode and the multi-core processing mode as a function of the number of tasks.

2. The electronic device of claim 1, further comprising:

a memory storing data of the electronic device.

3. The electronic device of claim 1, further comprising:

a bus connecting the processing component to the memory to enable accessing of the memory.

4. The electronic device of claim 1, wherein the processing component is a multiple-core processor.

5. The electronic device of claim 4, wherein a single core of the multiple-core processor is used during the single-core processing mode.

6. The electronic device of claim 4, wherein the multiple-core processor is one of a dual-core processor and a quad-core processor.

7. The electronic device of claim 1, wherein the processing component is a multiple-core processor and a single-core processor.

8. The electronic device of claim 7, wherein the multiple-core processor is used for the multi-core processor mode and the single-core processor is used for the single-core processor mode.

9. The electronic device of claim 1, wherein the processing component is a plurality of single-core processors.

10. The electronic device of claim 9, wherein at least two of the plurality of single-core processors are used for the multi-core processor mode and one of the plurality of single-core processors is used for the single-core processor mode.

11. A method, comprising:

determining a number of tasks running on an electronic device, the electronic device comprising a processing component configurable for one of a single-core processing mode and a multi-core processing mode; and

one of;

configuring the processor to the single-core processing mode when the number of tasks is one; and

configuring the processor to the multi-core processing mode when the number of tasks is more than one.

12. The method of claim 11, wherein the electronic device further comprises a memory storing data of the electronic device.

13. The method of claim 12, wherein the electronic device further comprises a bus connecting the processing component to the memory to enable accessing of the memory.

14. The method of claim 11, wherein processing component is a multi-core processor.

15. The method of claim 14, wherein a single core of the multi-core processor is used during the single-core processing mode.

16. The method of claim 11, wherein the processing component is a multiple-core processor and a single-core processor.

17. The method of claim 16, wherein the multiple-core processor is used for the multi-core processor mode and the single-core processor is used for the single-core processor mode.

18. The method of claim 11, wherein the processing component is a plurality of single-core processors.

19. The method of claim 18, wherein at least two of the plurality of single-core processors are used for the multi-core processor mode and one of the plurality of single-core processors is used for the single-core processor mode.

20. A computer readable storage medium including a set of instructions executable by a processor, the set of instructions operable to:

determine a number of tasks running on an electronic device, the electronic device comprising a processing component configurable for one of a single-core processing mode and a multi-core processing mode; and

one of;

configure the processor to the single-core processing mode when the number of tasks is one; and

configure the processor to the multi-core processing mode when the number of tasks is more than one.