Vertical LDMOS device and method for fabricating same

• US 20110272759A1
• Filed: 05/06/2010
• Published: 11/10/2011
• Est. Priority Date: 05/06/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Bol, Igor
• Granted Patent: US 8,299,527 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2256 through the applied layer
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body.

Claims

1. A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprising:

a trench within a semiconductor body, and a semiconductor substrate underlying said semiconductor body, said trench including sidewalls, a bottom portion, a dielectric material lining said trench and a diffusion agent layer lining said dielectric material;

a lightly doped drain region extending laterally from said sidewalls of said trench into said semiconductor body.

2. The vertically arranged LDMOS device of claim 1, further comprising an insulative material filling said trench.

3. The vertically arranged LDMOS device of claim 1, wherein said semiconductor body is of a first conductivity type, and said lightly doped drain region and said semiconductor substrate are of a second conductivity type.

4. The vertically arranged LDMOS device of claim 1, wherein said trench further comprises a gate electrode formed over said diffusion agent layer.

5. The vertically arranged LDMOS device of claim 1, wherein said trench extends into said semiconductor substrate.

6. The vertically arranged LDMOS device of claim 1, wherein said bottom portion of said trench is disposed above said semiconductor substrate.

7. The vertically arranged LDMOS device of claim 1, wherein said lightly doped drain region extends to said semiconductor substrate.

8. The vertically arranged LDMOS device of claim 1, wherein said semiconductor body comprises an epitaxial semiconductor layer.

9. A method for fabricating a vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprising:

forming a trench within a semiconductor body, said trench including sidewalls, a bottom portion, a dielectric material lining said trench and a diffusion agent layer lining said dielectric material;

diffusing impurities from said diffusion agent layer through said dielectric material to form a lightly doped drain region extending laterally from said sidewalls of said trench into said semiconductor body.

10. The method of claim 9, further comprising filling said trench with an insulative material.

11. The method of claim 9, wherein said semiconductor body is of a first conductivity type, and said lightly doped drain region and said semiconductor substrate are of a second conductivity type.

12. The method of claim 9, further comprising forming a gate electrode in said trench over said diffusion agent layer.

13. The method of claim 9, wherein said trench is extended into said semiconductor substrate.

14. The method of claim 9, wherein said bottom portion of said trench is disposed above said semiconductor substrate.

15. The method of claim 9, wherein said lightly doped drain region extends to said semiconductor substrate.

16. A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprising:

first and second trenches each extending into a semiconductor body, and a semiconductor substrate underlying said semiconductor body;

a first lightly doped drain region adjoining said first trench and a second lightly doped drain region adjoining said second trench;

wherein said first and second lightly doped drain regions are spaced laterally apart by said semiconductor body.

17. The vertically arranged LDMOS device of claim 16, wherein said first and second trenches each includes sidewalls, a bottom portion, a dielectric material lining each trench and a diffusion agent layer lining said dielectric material;

said first and second lightly doped drain regions extending laterally from said sidewalls of said trenches into said semiconductor body.

18. The vertically arranged LDMOS device of claim 16, wherein said semiconductor body is of a first conductivity type, and said first and second lightly doped drain regions and said semiconductor substrate are of a second conductivity type.

19. The vertically arranged LDMOS device of claim 16, wherein said first and second trenches extend into said semiconductor substrate.

20. The vertically arranged LDMOS device of claim 16, wherein said bottom portion of each of said first and second trenches is disposed above said semiconductor substrate.