SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20110272813A1
• Filed: 05/05/2011
• Published: 11/10/2011
• Est. Priority Date: 05/07/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: FURUTAKE, Naoya, SAITOU, Shinobu, HAYASHI, Yoshihiro, KAWAHARA, Jun, KUME, Ippei
• Granted Patent: US 8,759,212 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming an insulating film, including Si and C, over a substrate;

forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of said insulating film, over said insulating film; and

forming two or more concave portions, having different opening diameters, in said organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.

2. The method of manufacturing a semiconductor device as set forth in claim 1, wherein the ratio of the flow rate of said N-containing gas to the flow rate of said inert gas is 1 or greater.

3. The method of manufacturing a semiconductor device as set forth in claim 1, wherein the ratio of the flow rate of said fluorocarbon gas to the flow rate of said oxidant gas is equal to or greater than 1 and equal to or less than 5.

4. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said composition ratio of said organic silica film to said insulating film is 2 or greater.

5. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said N-containing gas includes at least one selected from a group consisting of nitrogen gas, ammonia gas, and amine gas.

6. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said fluorocarbon gas includes at least one selected from a group consisting of CF₄, CHF₃, CH₂F₂, CHF₃, C₂F₆, C₂H₂F₄, C₂H₄F₂, C₂F₄, C₂H₂F₂, C₃F₈, C₃H₂F₆, C₃H₄F₄, C₃H₆F₂, C₃F₆, C₃HF₅, C₃H₃F₃, C₃H₄F₂ or C₃H₅F.

7. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said oxidant gas includes at least one selected from a group consisting of O₂, CO₂, CH₃OH, C₂H₅OH, C₃H₇OH, N₂O, NO, N₂O₃, NO₂, N₂O₄ and N₂O₅.

8. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said insulating film includes SiC, SiCN, or SiOCN.

9. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said organic silica film is a porous insulating film, and the average vacancy diameter of said porous insulating film is less than 1 nm.

10. The method of manufacturing a semiconductor device as set forth in claim 1, wherein said organic silica film includes a compound having a cyclic organosiloxane structure represented by the following General Formula (1).

11. The method of manufacturing a semiconductor device as set forth in claim 10, wherein said compound having a cyclic organosiloxane structure is represented by the following Formula (2) or the following Formula (3).

12. A semiconductor device obtained by the method of manufacturing a semiconductor device as set forth in claim 1.

13. A semiconductor device comprising:

a substrate;

an insulating interlayer provided over said substrate;

a first metal film which is provided with a plurality of interconnect trenches within said insulating interlayer, and is buried in said interconnect trenches, respectively;

an insulating film, provided over said insulating interlayer, that includes Si and C;

an organic silica film, provided over said insulating film, that has a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of said insulating film; and

a second metal film which is provided with a first concave portion and a second concave portion having a larger opening diameter than that of said first concave portion in said organic silica film, and is buried in said first concave portion and said second concave portion, respectively,

wherein said second metal film and said first metal film are electrically connected to each other, and

wherein in the surface of said first metal film between said second metal film buried in said first concave portion and said second concave portion, respectively, and said first metal film, a peak equivalent to an oxide of metal included in said first metal film does not exist when measured by a transmission electron microscope and electron energy loss spectroscopy.

14. The semiconductor device as set forth in claim 13, wherein the composition ratio of said organic silica film to said insulating film is 2 or greater.

15. The semiconductor device as set forth in claim 13, wherein said insulating film includes SiC, SiCN, or SiOCN.

16. The semiconductor device as set forth in claim 13, wherein said organic silica film is a porous insulating film, and the average vacancy diameter of said porous insulating film is less than 1 nm.

17. The semiconductor device as set forth in claim 13, wherein said organic silica film includes a compound having a cyclic organosiloxane structure represented by the following General Formula (1).

18. The semiconductor device as set forth in claim 17, wherein said compound having a cyclic organosiloxane structure is represented by the following Formula (2) or the following Formula (3).

19. The semiconductor device as set forth in claim 13, wherein said metal is Cu, and said oxide is CuO.