SIGNAL GENERATOR FOR A BUILT-IN SELF TEST

• US 20110273197A1
• Filed: 05/07/2010
• Published: 11/10/2011
• Est. Priority Date: 05/07/2010
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Banerjee, Gaurab, Behera, Manas
• Application Number:
  US12/776,168
• Publication Number:
  US 20110273197A1
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2843 In-circuit-testing
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071

Abstract

An integrated circuit with Built-in Self Test (BiST) is described. The integrated circuit includes a signal generator used to perform a BiST on the integrated circuit. The integrated circuit also includes a local oscillator used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit.

Claims

1. An integrated circuit with Built-in Self Test (BiST), comprising:

a signal generator on the integrated circuit, wherein the signal generator is used to perform a BiST on the integrated circuit; and

a local oscillator on the integrated circuit used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit.

2. The integrated circuit of claim 1, wherein the local oscillator comprises a frequency synthesizer used for functions other than BiST functions on the integrated circuit.

3. The integrated circuit of claim 1, wherein the local oscillator comprises a radio frequency (RF) synthesizer used for RF transceiver functions.

4. The integrated circuit of claim 1, wherein the signal generator comprises one or more frequency dividers.

5. The integrated circuit of claim 4, wherein the one or more frequency dividers generate differential quadrature signals (I, I⁻

, Q, Q⁻

) in one or more frequency bands.

6. The integrated circuit of claim 4, wherein the one or more frequency dividers comprises a high frequency divider array and a low frequency divider array, wherein the high frequency divider array divides the frequency of a local oscillator signal and the low frequency divider array divides the frequency of an external signal, wherein the local oscillator signal is at a higher frequency than the external signal.

7. The integrated circuit of claim 4, wherein the signal generator further comprises one or more mixers and a summer.

8. The integrated circuit of claim 7, wherein the one or more mixers mix two or more signals to generate one or more test signals.

9. The integrated circuit of claim 8, wherein the two or more signals mixed are selected from a group consisting of one or more signals based on a local oscillator signal and one or more signals based on an external signal.

10. The integrated circuit of claim 9, wherein the external signal is a digital clock reference signal.

11. The integrated circuit of claim 9, wherein one or more of the local oscillator signals are divided in frequency.

12. The integrated circuit of claim 9, wherein one or more of the external signals are divided in frequency.

13. The integrated circuit of claim 8, wherein the two or more signals to be mixed are selected by one or more multiplexers included in the integrated circuit.

14. The integrated circuit of claim 8, wherein the amplitude of the one or more test signals is adjusted by an amplifier/attenuator module included in the integrated circuit.

15. The integrated circuit of claim 8, wherein the two or more signals are selected and mixed in order to produce frequency variation in the one or more test signals.

16. The integrated circuit of claim 15, wherein the frequency variation is a frequency sweep over a given range of frequencies.

17. The integrated circuit of claim 8, wherein the two or more signals are selected and mixed in order to produce a frequency offset from the local oscillator signal in the one or more test signals.

18. The integrated circuit of claim 17, wherein the frequency offset in the one or more test signals is used to conduct down-conversion measurements.

19. The integrated circuit of claim 14, wherein the amplitude of the one or more test signals is varied to produce an amplitude sweep in the one or more test signals, wherein the amplitude sweep is selected from the group consisting of a linear amplitude sweep and a logarithmic amplitude sweep.

20. The integrated circuit of claim 14, wherein the amplitude of the one or more test signals is varied to produce an offset in differential outputs between two or more test signals.

21. The integrated circuit of claim 20, wherein the offset in differential outputs between the two or more test signals is used to measure one or more circuit imbalances.

22. The integrated circuit of claim 8, wherein the two or more signals are selected and mixed in order to produce test signals that are two-tone signals.

23. The integrated circuit of claim 8, wherein the one or more test signals are used to conduct third-order input intercept point (IIP3) measurements.

24. The integrated circuit of claim 8, wherein the two or more signals are selected and mixed in order to generate a test signal selected from the group consisting of:

an upper sideband (USB) signal, a lower sideband (LSB) signal, a double sideband signal (DSB) and a double sideband-suppressed carrier (DSB-SC) signal.

25. The integrated circuit of claim 8, wherein the one or more test signals are differential output signals.

26. A method for generating signals for a Built-in Self Test (BiST), comprising:

generating, on an integrated circuit, a local oscillator signal;

receiving an external signal; and

mixing, on the integrated circuit, two or more signals to generate one or more test signals for a BiST.

27. The method of claim 26, further comprising dividing, on the integrated circuit, the frequency of the local oscillator signal and the external signal into one or more frequency bands.

28. The method of claim 26, further comprising selecting, on the integrated circuit the two or more signals for mixing to generate one or more test signals.

29. The method of claim 28, wherein the two or more signals for mixing comprise differential quadrature signals (I, I⁻

, Q, Q⁻

).

30. The method of claim 28, further comprising varying, on the integrated circuit, the amplitude of the one or more test signals.

31. The method of claim 26, wherein the local oscillator comprises a radio frequency (RF) synthesizer used for RF transceiver functions.

32. The method of claim 26, wherein the external signal is a digital clock reference signal.

33. The method of claim 26, wherein the local oscillator signal is at a higher frequency than the external signal.

34. The method of claim 28, wherein the two or more signals are selected and mixed in order to produce frequency variation in the one or more test signals.

35. The method of claim 34, wherein the frequency variation is a frequency sweep over a given range of frequencies.

36. The method of claim 28, wherein the two or more signals are selected and mixed in order to produce a frequency offset from the local oscillator signal in the one or more test signals.

37. The method of claim 36, wherein the frequency offset in the one or more test signals is used to conduct down-conversion measurements.

38. The method of claim 30, wherein the amplitude of the test signals are varied to produce an amplitude sweep in the one or more test signals, wherein the amplitude sweep is selected from the group consisting of a linear amplitude sweep and a logarithmic amplitude sweep.

39. The method of claim 30, wherein the amplitude of the one or more test signals are varied in order to produce an offset in differential outputs between two or more of the test signals.

40. The method of claim 39, wherein the offset in differential outputs between the two or more test signals is used to measure one or more circuit imbalances.

41. The method of claim 28, wherein the two or more signals are selected and mixed in order to produce test signals that are two-tone signals.

42. The method of claim 28, wherein the test signals are used to conduct third-order input intercept point (IIP3) measurements.

43. The method of claim 28, wherein the two or more signals are selected and mixed in order to generate a signal selected from the group consisting of:

an upper sideband (USB) signal, a lower sideband (LSB) signal, a double sideband signal (DSB) and a double sideband-suppressed carrier (DSB-SC) signal.

44. The method of claim 26, wherein the one or more test signals are differential output signals.

45. A computer-program product for generating signals for a Built-in Self Test (BiST), the computer-program product comprising a non-transitory computer-readable medium having instructions thereon, the instructions comprising:

code for generating a local oscillator signal;

code for receiving an external signal; and

code for mixing two or more signals to generate one or more test signals.

46. The computer-program product of claim 45, wherein the instructions further comprise code for varying the amplitude of the one or more test signals.

47. The computer-program product of claim 45, wherein the instructions further comprise code for varying the frequency of the one or more test signals.

48. An apparatus for generating signals for a Built-in Self Test (BiST), comprising:

means for generating a local oscillator signal;

means for receiving an external signal; and

means for mixing two or more signals to generate one or more test signals.

49. The apparatus of claim 48, further comprising means for varying the amplitude of the one or more test signals and means for varying the frequency of the one or more test signals.