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LOW POWER DIGITAL PHASE LOCK LOOP CIRCUIT

  • US 20110273210A1
  • Filed: 05/07/2010
  • Published: 11/10/2011
  • Est. Priority Date: 05/07/2010
  • Status: Active Grant
First Claim
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1. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:

  • a phase detecting portion operable to output a compared signal based on the reference clock signal;

    an oscillator operable to output an oscillator clock signal;

    a feedback divider operable to output a divided signal based on the oscillator clock signal; and

    a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state,wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state, andwherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state.

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