LOW POWER DIGITAL PHASE LOCK LOOP CIRCUIT
First Claim
1. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:
- a phase detecting portion operable to output a compared signal based on the reference clock signal;
an oscillator operable to output an oscillator clock signal;
a feedback divider operable to output a divided signal based on the oscillator clock signal; and
a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state,wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state, andwherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state.
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Accused Products
Abstract
A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.
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Citations
20 Claims
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1. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:
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a phase detecting portion operable to output a compared signal based on the reference clock signal; an oscillator operable to output an oscillator clock signal; a feedback divider operable to output a divided signal based on the oscillator clock signal; and a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state, wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state, and wherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A digital phase lock loop circuit for use with a reference clock signal, said digital phase lock loop circuit comprising:
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a phase detecting portion operable to output a compared signal based on the reference clock signal; an oscillator operable to output an oscillator clock signal; a feedback divider operable to output a divided signal based on the oscillator clock signal; a switching portion operable to output a first feedback signal based on the oscillator clock signal when in a first state, to output a second feedback signal based on the divided signal when in a second state and to switch from the first state to the second state; a time-to-digital portion operable to output a digital delay signal based on the compared signal; a loop filter portion operable to output a filtered delay signal based on the digital delay signal; a synchronization flip-flop operable to output a synchronized signal based on the oscillator clock signal and the divided signal; a lock detector portion operable to detect a parameter based on the reference clock and to switch said switching portion from the first state to the second state based on the detected parameter; an input divider operable to output a select signal; an output divider operable to output a divided output signal; and an error corrector operable to output a corrected digital delay signal based on the digital delay signal and the select signal, wherein said phase detecting portion is further operable to receive a first input feedback signal, based on the first feedback signal, when said switching portion is in the first state, wherein said phase detecting portion is further operable to receive a second input feedback signal, based on the second feedback signal, when said switching portion is in the second state, wherein said phase detecting portion is further to operable to output the compared signal based on the reference clock signal and the first input feedback signal when said switching portion is in the first state, wherein said phase detecting portion is further to operable to output the compared signal based on the reference clock signal and the second input feedback signal when said switching portion is in the second state, wherein said oscillator is operable to output the oscillator clock signal based on the filtered delay signal, wherein said switching portion is operable to output the second feedback signal based as the synchronized signal when in a second state, wherein said error corrector comprises a demultiplexer, an averager, an adder and a multiplexer, wherein said demultiplexer is arranged to receive the digital delay signal and the select signal, and is operable to output a first phase difference signal and a second phase difference signal based on the select signal, wherein said averager is operable to receive the second phase difference signal and to output an expected phase difference signal based on the second phase difference signal, wherein said adder is operable to output a residual phase difference signal based on the second phase difference signal and the expected phase difference signal, and wherein said multiplexer is operable to output, based on the select signal, a corrected digital delay signal based on the first phase difference signal and the residual phase difference signal.
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14. A method of digitally phase locking an output signal with a reference clock signal, said method comprising:
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outputting, by way of a phase detecting portion, a compared signal based on the reference clock signal; outputting, by way of an oscillator, an oscillator clock signal; outputting, by way of a feedback divider, a divided signal based on the oscillator clock signal; outputting, by way of a switching portion, a first feedback signal based on the oscillator clock signal when the switching portion is in a first state; outputting, by way of the switching portion, a second feedback signal based on the divided signal when the switching portion is in a second state; switching the switching portion from the first state to the second state; receiving, at an input of the phase detecting portion, a first input feedback signal;
based on the first feedback signal, when the switching portion is in the first state; andreceiving, at the input of the phase detecting portion, a second input feedback signal, based on the second feedback signal, when the switching portion is in the second state. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification