POWER CONTROL OF RECONFIGURABLE OUTPHASING CHIREIX AMPLIFIERS AND METHODS

• US 20110273236A1
• Filed: 03/21/2011
• Published: 11/10/2011
• Est. Priority Date: 05/04/2010
• Status: Active Grant

• Current Assignee: Ampleon Netherlands B.V. (Ampleon Coöperatief UA)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Heijden, Mark van der, Apostolidou, Melina, Vromans, Jan Sophia, Acar, Mustafa
• Granted Patent: US 8,174,322 B2
• Time in Patent Office: Days
• US Class Current: 330/295
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals

Abstract

Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L₁C₁, L₂C₂), a broadband combiner having Chireix compensation elements, and an impedance matching filter. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described. In some embodiments, a variable supply voltage may power the transistor circuitry based on the desired output power of the Chireix power amplifier. In some embodiments, the variable supply voltage may depend upon an out-phasing angle between the two drivers in the transistor circuitry.

Claims

1. An integrated digital Chireix power amplifier device comprising:

a power transistor circuit comprising;

a plurality of power transistors receiving a variable supply voltage, and

a shunt-series circuit, wherein the power transistor circuit produces an output power proportional to the variable supply voltage;

a broadband combiner having Chireix compensation elements; and

an impedance matching filter, wherein the power transistor circuit, the broadband combiner, and the impedance matching filter are integrated in a unified package.

2. The power amplifier device of claim 1, wherein the broadband combiner comprises a fixed broadband network and further wherein the power amplifier can be reconfigured for different frequency bands by adjusting the duty cycle of at least one of the plurality of power transistors.

3. The power amplifier device of claim 1, wherein the broadband combiner comprises a Marchand balun having a phase angle of less than 90 degrees.

4. The power amplifier device of claim 3, wherein the broadband combiner is configured to provide a constant real impedance level across a bandwidth of interest, and further wherein the broadband combiner further comprises a low-pass LC filter provided at an output node of the broadband combiner to provide additional impedance matching and establishing quality factors for a class-E operation of the power amplifier.

5. The power amplifier device of claim 1, wherein the variable supply voltage produced by a pre-driver comprises a square wave signal with a variable peak voltage (V_peak).

6. The power amplifier device of claim 5, wherein the variable supply voltage produced by a pre-driver includes a non-zero rising period (t_r) and falling period (t_f), wherein a sum of the rising period and falling period is less than 20% of a peak voltage period (t_peak).

7. The power amplifier device of claim 1, further comprising:

an input circuit that provides the variable supply voltage to the plurality of power transistors, the input circuit comprising;

a digital signal processor (DSP) that receives pairs of in-phase (I) and quadrature phase (Q) signals and produces a baseband envelope (A) for the variable supply voltage based on the (I, Q) values.

8. The power amplifier device of claim 7, wherein the input circuit further comprises:

a first block that provides the (I, Q) values comprising;

a base band (BB) circuit, and

a digital up-conversion (DUC) circuit.

9. The power amplifier device of claim 7, wherein the input circuit further comprises:

an RF modulator that receives a phase-modulated signal produced by the DSP and produces constant-amplitude phase-modulated signals for the plurality of power transistors.

10. The power amplifier device of claim 9, wherein the plurality of power transistors have a gain (G), and the power transistor circuit produces an output voltage (v_out) according to the equation:

v_out=GA·

cos(φ

(t)+ω

_ct).

11. A method of driving an integrated Chireix power amplifier device, the method comprising:

providing a power transistor circuit comprising a plurality of power transistors receiving a variable supply voltage and a shunt-series circuit, a broadband combiner having Chireix compensation elements, and an impedance matching filter in a unified package;

driving variable capacitors in the broadband combiner so as to enable reconfiguring of the power amplifier structure; and

producing, by the power transistor circuit, an output power proportional to the variable supply voltage.

12. The method of claim 11, further comprising:

reconfiguring the broadband combiner for operation at different frequency bands by adjusting the duty cycle of at least one of the plurality of power transistors, wherein the broadband combiner comprises a fixed broadband network.

13. The method of claim 11, wherein the broadband combiner comprises a Marchand balun having a phase angle of less than 90 degrees.

14. The method of claim 13, further comprising:

providing a constant real impedance level across a bandwidth of interest; and

providing a low-pass LC filter at an output node of the broadband combiner, wherein the low-pass LC filter

provides additional impedance matching, and

establishes quality factors for a class-E operation of the power amplifier.

15. The method of claim 11, wherein the variable supply voltage comprises a square wave signal with a variable peak voltage (V_peak).

16. The method of claim 15, wherein the variable supply voltage includes a non-zero rising period (t_r) and falling period (t_f), wherein a sum of the rising period and falling period is less than 20% of a peak voltage period (t_peak).

17. The method of claim 11, further comprising:

receiving, by a digital signal processor (DSP) in an input circuit, pairs of in-phase (I) and quadrature-phase (Q) signals; and

producing, by the DSP, a baseband envelope (A) for the variable supply voltage based on the (I, Q) values; and

providing, by the input circuit, the variable supply voltage to the plurality of power transistors.

18. The method of claim 17, further comprising:

providing, by a first block in the input circuit comprising a base band (BB) circuit and a digital up-conversion (DUG) circuit, the (I, Q) values.

19. The method of claim 17, further comprising:

receiving, by an RF modulator in the input circuit, a phase-modulated signal produced by the DSP; and

producing, by the RF modulator, constant-amplitude phase-modulated signals for the plurality of power transistors.

20. The method of claim 19, wherein the plurality of power transistors have a gain (G), and the power transistor circuit produces an output voltage (v_out) according to the equation:

v_out=GA·

cos(φ

(t)+ω

_ct).