RECORDING HEAD

• US 20110273497A1
• Filed: 04/27/2011
• Published: 11/10/2011
• Est. Priority Date: 05/10/2010
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Yamamoto, Akira, Iwanaga, Shuzo
• Granted Patent: US 9,186,897 B2
• Time in Patent Office: Days
• US Class Current: 347/9
• CPC Class Codes: B41J 2/14072 Electrical connections, e.g. details on electrodes, connecting the chip to the outside...
• CPC Class Codes: B41J 2/155 for line printing
• CPC Class Codes: B41J 2202/20 Modules

Abstract

A recording head includes: a recording element substrate having a recording element and a logic circuit cofigured to control driving of the recording element; and an electric wiring member cofigured to provide a wiring layer that has a first group of a plurality of terminals, a second group of a plurality of terminals, and a plurality of signal lines configured to connect the first group of terminals to the second group of terminals; wherein the plurality of signal lines includes a plurality of logic signal lines including a logic power source line, a logic ground line, and at least first and second logic signal lines, and wherein, on the wiring layer, a line pattern connected to one of the logic power source line and the logic ground line is disposed along the first and second logic signal lines.

Claims

1. A recording head, comprising:

a recording element substrate having a recording element and a logic circuit cofigured to control driving of the recording element; and

an electric wiring member cofigured to provide a wiring layer that has a first group of a plurality of terminals, a second group of a plurality of terminals, and a plurality of signal lines configured to connect the first group of terminals to the second group of terminals;

wherein the plurality of signal lines includes a plurality of logic signal lines including a logic power source line, a logic ground line, and at least first and second logic signal lines, and

wherein, on the wiring layer, a line pattern connected to one of the logic power source line and the logic ground line is disposed along the first and second logic signal lines.

2. The recording head according to claim 1, wherein the line pattern is disposed between the first logic signal line and the second logic signal line on the wiring layer.

3. The recording head according to claim 1, wherein the terminals of the second group are arranged adjacent to one another, and are connected to the logic signal lines respectively.

4. The recording head according to claim 1, wherein the terminals of the first group are arranged adjacent to one another, and are connected at least to a driving power source line, and a driving ground line, in addition to the logic signal lines.

5. The recording head according to claim 1, wherein the first and second signal logic lines are clock signal lines or data signal lines.

6. The recording head according to claim 1, wherein the predetermined signal includes a signal that determines a period of time to drive the recording element.

7. The recording head according to claim 1, wherein the logic circuit includes a storing circuit configured to store a value of a data signal, and

wherein the predetermined signal includes a latch signal that controls the storing circuit.