ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME

• US 20110273949A1
• Filed: 05/06/2010
• Published: 11/10/2011
• Est. Priority Date: 05/06/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIN, Sung-Chieh, CHEN, Po-Hung, HUANG, Jiann-Tseng, HSU, Kuoyuan
• Granted Patent: US 8,427,857 B2
• Time in Patent Office: Days
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

Claims

1. A circuit, comprising:

a fuse coupled between a MOS transistor and a current source node; and

a sensing and control circuit coupled to a gate of the MOS transistor, the sensing and control circuit configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the first fuse, the modified programming signal having a pulse width based on a magnitude of a current through the fuse.

2. The circuit of claim 1, wherein the sensing and control circuit includes a pulse generator configured to provide an intermediate programming signal in response to receiving the programming pulse, the intermediate programming signal having a narrower pulse width than a pulse width of the programming pulse.

3. The circuit of claim 2, wherein the pulse generator provides the intermediate programming signal to a logic gate configured to generate the modified programming signal in response to receiving the intermediate programming signal.

4. The circuit of claim 3, wherein the sensing and control circuit includes a comparator circuit, the comparator circuit configured to

compare a voltage representation of a current flowing through the first fuse to a reference voltage, and

output a signal identifying that the voltage representation of the current flowing through the first fuse is less than the reference voltage.

5. The circuit of claim 4, wherein the voltage representation of the current flowing through the fuse is generated by an operational amplifier configured to sense the current flowing through the fuse.

6. The circuit of claim 5, wherein the operational amplifier includes a first input coupled to a first voltage source node and a second input configured to receive a voltage across the current source.

7. A method, comprising:

generating an intermediate programming pulse in response to receiving a programming pulse at a pulse generator; and

outputting a modified programming pulse to a gate of a transistor in response to receiving one of the intermediate programming pulse or a signal identifying that a current through a fuse has fallen below a threshold level, the modified programming pulse controlling the current through the fuse.

8. The method of claim 7, further comprising:

sensing the current through the fuse;

comparing a voltage representation of the current through the fuse to a reference voltage; and

outputting the signal identifying if the current through the fuse falls below the threshold level.

9. The method of claim 8, wherein the sensing of the current through the fuse is performed by an operational amplifier having a first input coupled to a voltage source node and a second input configured to receive a voltage across a current source.

10. The method of claim 8, wherein the comparison of the voltage representation of the current through the fuse to a reference voltage is performed at a comparator.

11. The method of claim 8, wherein the signal identifying if the current through the fuse falls below the threshold level and the intermediate programming signal are received at a logic gate.

12. The method of claim 8, wherein reference voltage is a voltage representation of a current threshold of the fuse.

13. The method of claim 7, wherein the intermediate programming pulse has a narrower pulse width than a pulse width of the programming pulse.

14. An integrated circuit, comprising:

a fuse coupled to a first MOS transistor and to a voltage supply node; and

a programming circuit for providing a first programming signal to a gate of the MOS transistor for programming the fuse in response to receiving one of a second programming signal or a signal identifying that a current through the fuse has fallen below a threshold level.

15. The integrated circuit of claim 14, wherein the programming circuit includes an OR gate configured to output the first programming signal to the gate of the MOS transistor in response to receiving one of the second programming signal at a first input or the signal identifying the current through the resistor falls below the threshold at a second input.

16. The integrated circuit of claim 14, wherein the second programming signal is generated by a pulse generator in response to receiving a third programming signal.

17. The integrated circuit of claim 14, wherein the OR gate receives the signal identifying that the current through the fuse falls below the threshold from a comparator.

18. The integrated circuit of claim 17, wherein the comparator has a first input for receiving the reference voltage and a second input coupled to an output of an operational amplifier.

19. The integrated circuit of claim 18, wherein the operational amplifier has a first input coupled to the first voltage supply node and a second input for receiving the voltage across the current source.

20. The integrated circuit of claim 19, wherein the operational amplifier is configured to sense the current through the fuse and output a voltage representation of the sensed current to the comparator.

21. The integrated circuit of claim 14, wherein the first and second programming signals have narrower pulse widths than a pulse width of the first programming signal.