RE-CONFIGURABLE TEST CIRCUIT, METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT, APPARATUS, METHOD AND COMPUTER PROGRAM FOR SETTING UP AN AUTOMATED TEST EQUIPMENT

• US 20110276302A1
• Filed: 11/11/2008
• Published: 11/10/2011
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Rivoir, Jochen
• Granted Patent: US 8,838,406 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/31903 tester configuration
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Claims

1. A re-configurable test circuit for use in an automated test equipment, the test circuit comprising:

a test processor;

a programmable logic device; and

a pin electronics circuit configured to provide an interface between the re-configurable test circuit and a device-under-test;

wherein the test processor comprises a timing circuit configured to provide one or more adjustable-timing signals comprising an adjustable timing;

wherein the programmable logic device is configured to implement a state machine, a state sequence of which is dependent on one or more input signals received via the pin electronics circuit;

wherein the re-configurable test circuit is configured to acquire, using the programmable logic device, an output signal, which output signal is dependent on a current or previous state of the state machine, and which output signal is indicative of a signal to be output by the pin electronics circuit, in response to the one or more input signals received from the pin electronics circuit; and

wherein the test processor is coupled to the programmable logic device and wherein the test processor is configured to adjust, using the one or more adjustable-timing signals, a timing used in a signal processing path, wherein the signal processing path comprises a path through the programmable logic device to provide the output signal in dependence on the one or more input signals.

2. The re-configurable test circuit according to claim 1, wherein the test processor is configured to sample one or more signals provided by the pin electronics circuit in response to the one or more adjustable timing signals, to acquire the one or more input signals of the programmable logic device, or

wherein the test processor is configured to sample a signal provided by the programmable logic device in response to one of the adjustable-timing signals, to acquire the output signal.

3. The re-configurable test circuit according to claim 1, wherein the test processor is configured to sample a signal provided by the pin electronics circuit in response to one or more of the adjustable-timing signals, to acquire a sample of the input signal, and to provide the sample of the input signal to the programmable logic device.

4. The re-configurable test circuit according to claim 3, wherein the test processor comprises a first-in-first-out memory configured to buffer a plurality of samples of the signal provided by the pin electronics circuit prior to forwarding the samples to the programmable logic device.

5. The re-configurable test circuit according to claim 1, wherein the test processor is configured to sample a signal provided by the pin electronics circuit in response to a first of the adjustable-timing signals, to acquire a sample of the signal provided by the pin electronics circuit, and to provide the sample of the input signal to the programmable logic device in response to a second of the adjustable timing signals,

wherein the test processor is configured to adjust a timing relationship between the first of the adjustable-timing signals and the second of the adjustable-timing signals.

6. The re-configurable test circuit according to claim 1, wherein the test processor is configured to sample a data-out signal provided by the programmable logic device in response to one or more of the adjustable-timing signals, to acquire a sample of the data-out signal provided by the programmable logic device, and to provide the sample of the data-out signal as the output signal.

7. The re-configurable test circuit according to claim 6, wherein the test processor comprises a first-in-first-out memory configured to buffer a plurality of samples of the data-out signal provided by the programmable logic device prior to forwarding the samples of the data-out signal provided by the programmable logic device as the output signal.

8. The re-configurable test circuit according to claim 1, wherein the test processor is configured to sample a data-out signal provided by the programmable logic device in response to a first of the adjustable-timing signals, to acquire a sample of the data-out signal provided by the programmable logic device, and to provide the sample of the data-out signal provided by the programmable logic device in response to a second of the adjustable timing signals,

wherein the test processor is configured to adjust a timing relationship between the first of the adjustable-timing signals and the second of the adjustable-timing signals.

9. The re-configurable test circuit according to claim 1, wherein the test processor comprises a first-in-first-out memory configured to buffer a plurality of samples of the signal provided by the programmable logic device prior to forwarding the samples to the pin electronics circuit.

10. The re-configurable test-circuit according to claim 1, wherein the programmable logic device is configured to provide, using the state machine, a driver-activation signal indicating whether a driver of the pin electronics circuit should be activated or not, and

wherein the test processor is configured to sample the driver-activation signal provided by the programmable logic device in response to one or more of the adjustable-timing signals, to acquire a sample of the driver-activation signal provided by the programmable logic device, and to provide the sample of the driver-activation signal to an enable input of the pin electronics circuit.

11. The re-configurable test circuit according to claim 10, wherein the test processor comprises a first-in-first-out memory configured to buffer a plurality of samples of the driver-activation signal provided by the programmable logic device prior to forwarding the samples of the driver-activation signal provided by the programmable logic device to the enable input of the pin electronics circuit.

12. The re-configurable test circuit according to claim 1, wherein the test processor is configured to sample a driver activation signal provided by the programmable logic device in response to a first of the adjustable-timing signals, to acquire a sample of the driver-activation signal provided by the programmable logic device, and to provide the sample of the driver-activation signal provided by the programmable logic device in response to a second of the adjustable timing signals,

wherein the test processor is configured to adjust a timing relationship between the first of the adjustable-timing signals and the second of the adjustable-timing signals.

13. The re-configurable test circuit according to claim 1, wherein the test processor is circuited between the pin electronics circuit and the programmable logic device;

and

wherein the test processor is configured to forward signals originating from the pin electronics circuit to the programmable logic device, and to adjust a timing of the forwarding of signals originating from the pin electronics circuit to the programmable logic device;

or

wherein the test processor is configured to forward signals originating from the programmable logic device to the pin electronics circuit, and to adjust a timing of the forwarding of signals originating from the programmable logic device to the pin electronics circuit.

14. The re-configurable test circuit according to claim 1, wherein the test processor is configured to forward one or more signals from the pin-electronics circuit to the programmable logic device, and

wherein the test processor is configured to adjustably shift a timing of the one or more signals forwarded from the pin electronics circuit to the programmable logic device.

15. The re-configurable test circuit according to claim 1, wherein the test processor is configured to forward one or more signals from the programmable logic device to the pin electronics circuit, and

wherein the test processor is configured to adjustably shift a timing of the one or more signals forwarded from the programmable logic device to the pin electronics circuit.

16. The re-configurable test circuit according to claim 1, wherein the test processor is coupled to the programmable logic device to provide at least one of the one or more adjustable-timing signals to the programmable logic device, to determine a timing of the programmable logic device.

17. The re-configurable test circuit according to claim 1, wherein the programmable logic device comprises a clocked circuit to provide the output signal on the basis of the one or more input signals received from the pin electronics circuit;

and

wherein the test processor is coupled to the programmable logic device to provide at least one of the one or more adjustable-timing signals to the programmable logic device, to determine a timing of the clocked circuit of the programmable logic device.

18. The re-configurable test circuit according to claim 16, wherein the programmable logic device comprises a clocked storage device configured to capture at least one of the one or more programmable logic device input signals received from the pin electronics circuit;

and

wherein one of the adjustable-timing signals is coupled to a clock input of the clocked storage device to allow for an adjustment of time instances at which the clocked storage device captures the programmable logic device input signal.

19. The re-configurable test circuit according to claim 16, wherein the programmable logic device comprises a clocked storage device configured to gate the programmable logic device output signal;

and

wherein one of the adjustable-timing signals is coupled to a clock input of the clocked storage device to allow for an adjustment of time instances at which the clocked storage device updates the programmable logic device output signal.

20. The re-configurable test circuit according to claim 16, wherein the state machine of the programmable logic device is a clocked state machine;

wherein the state machine comprises one or more clocked storage elements; and

wherein one of the adjustable-timing signals is coupled to the one or more clocked storage elements of the state machine, to allow for an adjustment of the timing of the clocked state machine.

21. The re-configurable test circuit according to claim 16, wherein the re-configurable test circuit is configured to forward at least one of the adjustable-timing signals both to the programmable logic device, to determine a timing of the programmable logic device, and to the pin electronics circuit to output the adjustable-timing signal to a device-under-test via the pin electronics circuit;

or

wherein the reconfigurable test circuit is switchable to selectably forward at least one of the adjustable-timing signals to the programmable logic device, to determine the timing of the programmable logic device, or to the pin electronics circuit, to output the adjustable-timing signal to a device-under-test via the pin electronics circuit.

22. The re-configurable test circuit according to claim 16, wherein the programmable logic device is coupled to a bit-stream-output of the test processor to receive the adjustable-timing signal;

and

wherein the test processor comprises a data sequencer configured to generate a bit stream comprising a programmable bit sequence at the bit stream output in dependence on a bit stream description describing the programmable sequence of bits of the bit stream.

23. The re-configurable test circuit according to claim 22, wherein the test processor further comprises a drive formatter configured to adjust a timing of edges of the bit stream at the bit stream output.

24. The re-configurable test circuit according to claim 16, wherein the programmable logic device is configured to receive the one or more adjustable-timing signals from a device-under-test bit-stream-output-channel of the test processor, wherein the device-under-test bit-stream-output-channel is adapted to provide a bit stream comprising a programmable bit sequence and a programmable timing.

25. The re-configurable test circuit according to claim 16, wherein the programmable logic device is configured to receive one or more adjustable-timing signals from a device-under-test bit-stream-output-channel of the test processor, to receive an instruction from the test processor to control a generation of the output signal provided to the pin electronics circuit.

26. The re-configurable test circuit according to claim 16, wherein the programmable logic device is configured to receive one or more adjustable-timing signals from a device-under-test bit-stream-output-channel of the test processor, to receive data from the test processor to control a generation of the output signal provided to the pin electronics circuit.

27. The re-configurable test circuit according to claim 16, wherein the programmable logic device is configured to provide a programmable logic device result signal in dependence on one or more of the input signals received from the pin electronics circuit or from the test processor;

and

wherein the test processor is configured to receive the programmable logic device result signal.

28. The re-configurable test circuit according to claim 27, wherein the test processor is configured to receive the programmable logic device result signal via a device-under-test bit-stream-input-channel;

and

wherein the device-under-test bit-stream-input-channel is adapted to compare the programmable logic device result signal with a programmable reference bit sequence.

29. The re-configurable test circuit according to claim 28, wherein the device-under-test bit-stream-input-channel comprises a receive formatter configured to determine a timing of the programmable logic device result signal.

30. The re-configurable test circuit according to claim 28, wherein the re-configurable test circuit is switchable to selectably couple the device-under-test bit-stream-input-channel of the test processor to the pin electronics circuit, to receive a device-under-test signal bypassing the programmable logic device, or to the programmable logic device, to receive the programmable logic device result signal.

31. The re-configurable test circuit according to claim 27, wherein the test processor is configured to trigger a capture of data in response to the programmable logic device result signal, or to stop a capture of data in response to the programmable logic device result signal.

32. The re-configurable test circuit according to claim 27, wherein the programmable logic device is configured to provide the programmable logic device result signal such that the programmable logic device result signal comprises a protocol information describing the communication protocol of the input signal received by the programmable logic device from the pin electronics circuit;

and

wherein the test processor is configured to capture the protocol information, to react in response to the protocol information, or to analyze the protocol information.

33. The re-configurable test circuit according to claim 27, wherein the programmable logic device is configured to provide the programmable logic device result signal such that the programmable logic device result signal comprises a data information describing a data content of the input signal;

and

wherein the test processor is configured to capture the data information, to react in response to the data information, or to analyze the data information.

34. The re-configurable test circuit according to claim 16, wherein the test processor is configured to receive the output signal provided to the pin electronics circuit by the programmable logic device, to capture said output signal, or to determine a timing of said output signal.

35. The re-configurable test circuit according to claim 16, wherein the re-configurable test circuit is configured to loop a programmable logic device output signal, output by the programmable logic device to the pin electronics circuit, back to an input of the test processor.

36. The re-configurable test circuit according to claim 16, wherein the test processor is configured to output a stimulus bit pattern to an input of the programmable logic device;

to receive a response signal, which is provided to the pin electronics circuit by the programmable logic device in response to the stimulus bit pattern; and

to determine a timing relationship between the stimulus bit pattern and the response signal.

37. The re-configurable test circuit according to claim 16, wherein the re-configurable test circuit is switchable to selectably operate

in a vector mode, in which vector mode the test processor is configured to generate a bit pattern and to provide the bit pattern to a bit pattern output, and in which vector mode the bit pattern output of the test processor is coupled to the pin electronics circuit, to output the generated bit pattern at a given terminal of a device-under-test connection of the pin electronics circuit, which device-under-test connection is connectable to a device-under-test;

or

in a protocol mode, in which protocol mode an output of the programmable logic device is coupled to the pin electronics circuit, to output the programmable logic device output signal at the given terminal of the device-under-test connection of the pin electronics circuit.

38. The re-configurable test circuit according to claim 37, wherein the test processor and the programmable logic device are configured to exchange, when operating in the protocol mode, a timing information, a trigger information, a control information or a data information.

39. The re-configurable test circuit according to claim 16, wherein the programmable logic device is coupled to a plurality of test processor device-under-test channels, to receive a plurality of bit patterns from one or more device-under-test output channels or to provide a plurality of bit patterns to device-under-test input channels.

40. The re-configurable test circuit according to claim 1, wherein the programmable logic device is configured to emulate a communication protocol, to provide the output signal to the pin electronics circuit in response to the one or more input signals received from the pin electronics circuit in accordance with the communication protocol.

41. The re-configurable test circuit according to claim 1, wherein the programmable logic device is configured to emulate a behavior of a memory.

42. The re-configurable test circuit according to claim 1, wherein the programmable logic device is a complex programmable logic device or a field programmable gate array.

43. A method for operating an automated test equipment, the method comprising:

providing one or more adjustable-timing signals using a test processor;

implementing, using a programmable logic device, a state machine, a state sequence of which is dependent on one or more signals received via a pin electronics circuit, to acquire, using the programmable logic device, an output signal, which output signal is dependent on a current or previous state of the state machine, in response to the one or more signals received via the pin electronics circuit;

wherein a timing used in a signal processing, which signal processing is used to acquire the output signal, is adjusted in response to at least one of the one or more adjustable-timing signals.

44. The method according to claim 43, wherein the one or more adjustable timing signals are provided to the programmable logic device;

wherein the state sequence of the state machine is dependent on one or more signals received from the pin electronics circuit by the programmable logic device;

wherein the programmable logic device provides the output signal in response to the one or more signals received from the pin electronics circuit, such that the output signal is dependent on a current or previous state of the state machine; and

wherein the a timing of the programmable logic device is determined using at least one of the one or more adjustable-timing signals.

45. An apparatus for setting up an automated test equipment, the automated test equipment comprising a configurable test processor, a programmable logic device and a pin electronics circuit, the apparatus being adapted to:

configure the test processor to provide one or more adjustable-timing signals comprising an adjustable timing;

configure the programmable logic device to implement a state machine, a state sequence of which state machine is dependent on one or more input signals received via the pin electronics circuit,

to acquire, using the programmable logic device, an output signal to be output via the pin electronics circuit in response to the one or more signals received via the pin electronics circuit,

wherein the output signal is dependent on a current or previous state of the state machine; and

configure the automated test equipment, such that a timing used in a signal processing, which signal processing is used to acquire the output signal, is adjusted in response to at least one of the one or more adjustable-timing signals.

46. A method for setting up an automated test equipment, the automated test equipment comprising a configurable test processor, a programmable logic device and a pin electronics circuit, the method comprising:

configuring the programmable test processor to provide one or more adjustable-timing signals comprising an adjustable timing; and

configuring the programmable logic device to implement a state machine, a state sequence of which state machine is dependent on one or more input signals received via a pin electronics circuit

to acquire, using the programmable logic device, an output signal to be output via the pin electronics circuit in response to the one or more signals received via the pin electronics circuit,

wherein the output signal is dependent on a current or previous state of the state machine; and

wherein at least one of the adjustable-timing signals determines a timing used in a signal processing, which signal processing is used to generate the output signal.

47. A computer program for performing the method for operating an automated test equipment, the method comprising:

providing one or more adjustable-timing signals using a test processor;

implementing, using a programmable logic device, a state machine, a state sequence of which is dependent on one or more signals received via a pin electronics circuit, to acquire, using the programmable logic device, an output signal, which output signal is dependent on a current or previous state of the state machine, in response to the one or more signals received via the pin electronics circuit;

wherein a timing used in a signal processing, which signal processing is used to acquire the output signal, is adjusted in response to at least one of the one or more adjustable-timing signals,

when the computer program runs on a computer.

48. A computer program for performing the method wherein the one or more adjustable timing signals are provided to the to the programmable logic device;

wherein the state ‘

sequence of the state machine is dependent on one or more signals received from the pin electronics circuit by the programmable logic device;

wherein the programmable logic device provides the output signal in response to the one or more signals received from the pin electronics circuit, such that the output signal is dependent on a current or previous state of the state machine; and

wherein the a timing of the programmable logic device is determined using at least one of the one or more adjustable-timing signals,

when the computer program runs on a computer.

49. A computer program for performing the method for setting up an automated test equipment, the automated test equipment comprising a configurable test processor, a programmable logic device and a pin electronics circuit, the method comprising:

configuring the programmable test processor to provide one or more adjustable-timing signals comprising an adjustable timing; and

configuring the programmable logic device to implement a state machine, a state sequence of which state machine is dependent on one or more input signals received via a pin electronics circuit

to acquire, using the programmable logic device, an output signal to be output via the pin electronics circuit in response to the one or more signals received via the pin electronics circuit,

wherein the output signal is dependent on a current or previous state of the state machine; and

wherein at least one of the adjustable-timing signals determines a timing used in a signal processing, which signal processing is used to generate the output signal,

when the computer program runs on a computer.