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METHOD AND SYSTEM FOR A RFIC MASTER

  • US 20110276736A1
  • Filed: 07/19/2011
  • Published: 11/10/2011
  • Est. Priority Date: 02/14/2006
  • Status: Active Grant
First Claim
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1. A method for handling operation of circuitry, the method comprising:

  • configuring from within a chip, an on-chip programmable device that functions as a master on a bus, wherein at least one interface to another device is coupled to said bus; and

    controlling at least one said another device coupled to said at least one interface via at least one signal generated by said on-chip programmable device, wherein said at least one generated signal is communicated via said bus when said on-chip programmable device receives an input timer signal.

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