METHOD AND SYSTEM FOR A RFIC MASTER

• US 20110276736A1
• Filed: 07/19/2011
• Published: 11/10/2011
• Est. Priority Date: 02/14/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: du Preez, Andrew, Hayem, Frederic, Conroy, Johan (Hendrik), Botha, Louis
• Granted Patent: US 8,161,217 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Abstract

Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

Claims

1. A method for handling operation of circuitry, the method comprising:

configuring from within a chip, an on-chip programmable device that functions as a master on a bus, wherein at least one interface to another device is coupled to said bus; and

controlling at least one said another device coupled to said at least one interface via at least one signal generated by said on-chip programmable device, wherein said at least one generated signal is communicated via said bus when said on-chip programmable device receives an input timer signal.

2-30. -30. (canceled)