SOFTWARE MANAGEMENT WITH HARDWARE TRAVERSAL OF FRAGMENTED LLR MEMORY

• US 20110276747A1
• Filed: 05/05/2011
• Published: 11/10/2011
• Est. Priority Date: 05/07/2010
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Dhawan, Rajat R., Fuchs, Robert Jason, Thelen, Christian O., Xu, Hao, Kongelf, Michael A.
• Application Number:
  US13/101,947
• Publication Number:
  US 20110276747A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/1874 Buffer management

Abstract

Certain aspects of the present disclosure relate to a method and apparatus for processing wireless communications. According to certain aspects, a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block is generated. Each chunk holds LLR values for a code block of the transport block. The linked list is then provided to a hardware circuit for traversal. According to certain aspects, the hardware circuit may be an application specific integrated circuit (ASIC) processor or field programmable gate array (FPGA) configured to traverse the linked list of chunks of memory used to store LLR values.

Claims

1. A method for wireless communications, comprising:

generating a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block, wherein each chunk holds LLR values for a code block of the transport block; and

providing the linked list to a hardware circuit for traversal.

2. The method of claim 1, wherein LLR values for each code block are stored in one or more chunks of the linked list.

3. The method of claim 1, wherein the code blocks of the transport block comprise code blocks of different sizes.

4. The method of claim 1, wherein providing the linked list comprises:

setting a plurality of parameters, readable by the hardware circuit, for each chunk in the linked list.

5. The method of claim 4, wherein the plurality of parameters for each chunk comprises:

a next chunk field indicating a next chunk for a corresponding code block of the transport block.

6. The method of claim 5, wherein the next chunk field of a last chunk in a related set of linked chunks indicates a first chunk in the related set of linked chunks for the corresponding code block.

7. The method of claim 4, wherein the plurality of parameters for each chunk comprise:

a code block last field that indicates whether the chunk is a last chunk in a related set of linked chunks for a corresponding code block.

8. The method of claim 4, wherein the plurality of parameters for each chunk comprise:

a transport block last field that indicates whether the chunk is a last in a related set of linked chunks for the transport block.

9. The method of claim 4, wherein the plurality of parameters for each chunk comprise:

a size field indicating an amount of LLR values stored in the chunk.

10. The method of claim 4, wherein the plurality of parameters for each chunk comprise:

a next code block identifier indicating a chunk in which LLR values for a next code block of the transport block are stored.

11. The method of claim 10, wherein each chunk in a related set of linked chunks for a corresponding code block has the same next code block identifier.

12. The method of claim 1, wherein the hardware circuit comprises at least one of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a configurable logic block.

13. The method of claim 1, wherein the each chunk is substantially the same size.

14. An apparatus for wireless communications, comprising:

a logarithmic likelihood ratio (LLR) memory for storing logarithmic likelihood ratio (LLR) values of a transport block;

a linked list manager configured to generate a linked list of chunks of the LLR memory, wherein each chunk holds LLR values for a code block of the transport block; and

a hardware circuit configured to traverse the linked list as provided by the linked list manager.

15. The apparatus of claim 14, wherein LLR values for each code block are stored in one or more chunks of LLR memory of the linked list.

16. The apparatus of claim 14, wherein the code blocks of the transport block comprise code blocks of different sizes.

17. The apparatus of claim 14, wherein the linked list manager is further configured to set parameters, readable by the hardware circuit, for each chunk in the linked list.

18. The apparatus of claim 17, wherein the parameters comprise, for each chunk:

a next chunk field indicating a next chunk for a corresponding code block of the transport block.

19. The apparatus of claim 18, wherein the next chunk field of a last chunk in a related set of linked chunks indicates a first chunk in the related set of linked chunks for the corresponding code block.

20. The apparatus of claim 17, wherein the parameters for each chunk comprises:

a code block last field that indicates whether the chunk is a last chunk in a related set of linked chunks for a corresponding code block.

21. The apparatus of claim 17, wherein the parameters for each chunk comprise:

a transport block last field that indicates whether the chunk is a last in a related set of linked chunks for the transport block.

22. The apparatus of claim 17, wherein the parameters for each chunk comprise:

a size field indicating an amount of LLR values stored in the chunk.

23. The apparatus of claim 17, wherein the parameters for each chunk comprise:

a next code block identifier indicating a chunk in which LLR values for a next code block of the transport block are stored.

24. The apparatus of claim 23, wherein each chunk in a related set of linked chunks for a corresponding code block has the same next code block identifier.

25. The apparatus of claim 14, wherein the each chunk is substantially the same size.

26. The apparatus of claim 14, wherein the hardware circuit comprises at least one of an application specific integrated circuit (ASIC) a field programmable gate array (FPGA), and a configurable logic block.

27. An apparatus for wireless communications, comprising:

means for generating a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block, wherein each chunk holds LLR values for a code block of the transport block; and

means for providing the linked list to a hardware circuit for traversal.

28. The apparatus of claim 27, wherein LLR values for each code block are stored in one or more chunks of the linked list.

29. The apparatus of claim 27, wherein the code blocks of the transport block comprise code blocks of different sizes.

30. The apparatus of claim 27, wherein means for providing the linked list comprises:

means for setting a plurality of parameters, readable by the hardware circuit, for each chunk in the linked list.

31. The apparatus of claim 30, wherein the plurality of parameters for each chunk comprises:

a next chunk field indicating a next chunk for a corresponding code block of the transport block.

32. The apparatus of claim 31, wherein the next chunk field of a last chunk in a related set of linked chunks indicates a first chunk in the related set of linked chunks for the corresponding code block.

33. The apparatus of claim 30, wherein the plurality of parameters for each chunk comprise:

a code block last field that indicates whether the chunk is a last chunk in a related set of linked chunks for a corresponding code block.

34. The apparatus of claim 30, wherein the plurality of parameters for each chunk comprise:

a transport block last field that indicates whether the chunk is a last in a related set of linked chunks for the transport block.

35. The apparatus of claim 30, wherein the plurality of parameters for each chunk comprise:

a size field indicating an amount of LLR values stored in the chunk.

36. The apparatus of claim 30, wherein the plurality of parameters for each chunk comprise:

a next code block identifier indicating a chunk in which LLR values for a next code block of the transport block are stored.

37. The apparatus of claim 36, wherein each chunk in a related set of linked chunks for a corresponding code block has the same next code block identifier.

38. The apparatus of claim 27, wherein the hardware circuit comprises at least one of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a configurable logic block.

39. The apparatus of claim 27, wherein the each chunk is substantially the same size.

40. A computer-program product comprising a computer-readable medium having instructions stored thereon, the instructions executable by one or more processors for:

generating a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block, wherein each chunk holds LLR values for a code block of the transport block; and

providing the linked list to a hardware circuit for traversal.

41. The computer-program product of claim 40, wherein LLR values for each code block are stored in one or more chunks of the linked list.

42. The computer-program product of claim 40, wherein the code blocks of the transport block comprise code blocks of different sizes.

43. The computer-program product of claim 40, wherein the instructions for providing the linked list comprises instructions for:

setting a plurality of parameters, readable by the hardware circuit, for each chunk in the linked list.

44. The computer-program product of claim 43, wherein the plurality of parameters for each chunk comprises:

a next chunk field indicating a next chunk for a corresponding code block of the transport block.

45. The computer-program product of claim 44, wherein the next chunk field of a last chunk in a related set of linked chunks indicates a first chunk in the related set of linked chunks for the corresponding code block.

46. The computer-program product of claim 43, wherein the plurality of parameters for each chunk comprise:

a code block last field that indicates whether the chunk is a last chunk in a related set of linked chunks for a corresponding code block.

47. The computer-program product of claim 43, wherein the plurality of parameters for each chunk comprise:

a transport block last field that indicates whether the chunk is a last in a related set of linked chunks for the transport block.

48. The computer-program product of claim 43, wherein the plurality of parameters for each chunk comprise:

a size field indicating an amount of LLR values stored in the chunk.

49. The computer-program product of claim 43, wherein the plurality of parameters for each chunk comprise:

a next code block identifier indicating a chunk in which LLR values for a next code block of the transport block are stored.

50. The computer-program product of claim 49, wherein each chunk in a related set of linked chunks for a corresponding code block has the same next code block identifier.

51. The computer-program product of claim 40, wherein the hardware circuit comprises at least one of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a configurable logic block.

52. The computer-program product of claim 40, wherein the each chunk is substantially the same size.