Eliminating, Coalescing, or Bypassing Ports in Memory Array Representations

• US 20110276931A1
• Filed: 05/07/2010
• Published: 11/10/2011
• Est. Priority Date: 05/07/2010
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Mony, Hari, Baumgartner, Jason R., Kanzelman, Robert L., Case, Michael L.
• Granted Patent: US 8,336,016 B2
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

Mechanisms are provided in a design environment for eliminating, coalescing, or bypassing ports. The design environment comprises one mechanism to eliminate unnecessary ports in arrays using disabled and disconnected pin information. The design environment may comprise another mechanism to combine and reduce the number of array ports using address comparisons. The design environment may comprise another mechanism to combine and reduce the number of array ports using disjoint enable comparisons. The design environment may comprise one mechanism to combine and reduce the number of array ports using “don'"'"'t care” computations. The design environment may comprise another mechanism to reduce the number of array ports through bypassing write-to-read paths around arrays.

Claims

1. A method, in a data processing system, for minimizing memory array representations, the method comprising:

receiving, in the data processing system, an integrated circuit design having a memory array;

reducing, by the data processing system, a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and

performing, by the data processing system, synthesis or verification on the reduced integrated circuit design.

2. The method of claim 1, wherein reducing the number of ports in the memory array comprises:

identifying one or more ports in the memory array that can never be enabled or have no data pins connected; and

deleting the one or more ports.

3. The method of claim 2, wherein reducing the number of ports in the memory array further comprises:

responsive to a given port within the one or more ports being a read port, converting each arrayout of the given port to a random gate.

4. The method of claim 1, wherein reducing the number of ports in the memory array comprises:

identifying two or more ports in the memory array that have equivalent addresses; and

coalescing the two or more ports in the memory array.

5. The method of claim 4, wherein identifying two or more ports in the memory array that have equivalent addresses comprises identifying a given port and a higher precedence port, wherein the given port is an initialization port or a write port and wherein the higher precedence port is guaranteed to write the same address whenever the given port writes;

wherein coalescing the two or more ports in the memory array comprises eliminating the given port.

6. The method of claim 4, wherein identifying two or more ports in the memory array that have equivalent addresses comprises identifying a given port, wherein the given port is an initialization port or a write port, wherein an enable of the given port implies an enable of a higher precedence port, and wherein no intermediate port can concurrently write to a same address as the given port and the higher precedence port;

and

wherein coalescing the two or more ports in the memory array comprises using the higher priority port to subsume the given port.

7. The method of claim 4, wherein identifying two or more ports in the memory array that have equivalent addresses comprises identifying a first read port and a second read port, wherein the first read port and the second read port have equivalent addresses and an enable of one of the first read port or the second read port implies an enable of the other of the first read port or the second read port;

and

wherein coalescing the two or more ports in the memory array comprises merging the arrayouts of the implied one of the first read port or the second read port with the arrayouts of the other of the first read port or the second read port.

8. The method of claim 4, wherein identifying two or more ports in the memory array that have equivalent addresses comprises identifying a first read port and a second read port, wherein the first read port and the second read port have equivalent addresses, an enable of the first read port does not imply an enable of the second read port, and an enable of the second read port does not imply an enable of the first read port;

and

wherein coalescing the two or more ports in the memory array comprises creating a new read port and merging arrayouts of the first read port and the second read ports onto arrayouts of the new read port.

9. The method of claim 1, wherein reducing the number of ports in the memory array comprises:

identifying two or more ports in the memory array that have orthogonal enables; and

coalescing the two or more ports in the memory array.

10. The method of claim 9, wherein coalescing the two or more ports in the memory array comprises:

for initialization ports or write ports, migrating write pins from a lower-precedence port to a higher-precedence port as long as no intermediate port can concurrently write to the same address of the higher-precedence port.

11. The method of claim 9, wherein coalescing the two or more ports in the memory array comprises:

for a first read port and a second read port in the memory array, creating a new read port and merging arrayouts of the first read port and the second read ports onto arrayouts of the new read port.

12. The method of claim 1, wherein reducing the number of ports in the memory array comprises:

for each given read port, identifying a mask for which all connected arrayouts of the given read port are masked with respect to a fanout boundary;

identifying a first read port and a second read port a compliment of the mask of the first read port AND a compliment of the mask of the second read port are equivalent; and

merging the first read port and the second read port.

13. The method of claim 12, wherein merging the first read port and the second read port comprises creating a new read port and merging arrayouts of the first read port and the second read ports onto arrayouts of the new read port.

14. The method of claim 1, wherein reducing the number of ports in the memory array comprises:

responsive to a determination that the memory array is a write-before-read array, identifying a read port and a write port, wherein the write port address matches the read port and every time the read port is enabled, the write port is also enabled; and

for each connected write pin, merging a corresponding read pin onto the connected write pin.

15. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive, in the computing device, an integrated circuit design having a memory array;

reduce, by the computing device, a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and

perform, by the computing device, synthesis or verification on the reduced integrated circuit design.

16. The computer program product of claim 15, wherein reducing the number of ports in the memory array comprises:

identifying one or more ports in the memory array that can never be enabled or have no data pins connected; and

deleting the one or more ports.

17. The computer program product of claim 15, wherein reducing the number of ports in the memory array comprises:

identifying two or more ports in the memory array that have equivalent addresses; and

coalescing the two or more ports in the memory array.

18. The computer program product of claim 15, wherein reducing the number of ports in the memory array comprises:

identifying two or more ports in the memory array that have orthogonal enables; and

coalescing the two or more ports in the memory array.

19. The computer program product of claim 15, wherein reducing the number of ports in the memory array comprises:

for each given read port, identifying a mask for which all connected arrayouts of the given read port are masked with respect to a fanout boundary;

identifying a first read port and a second read port a compliment of the mask of the first read port AND a compliment of the mask of the second read port are equivalent; and

merging the first read port and the second read port.

20. The computer program product of claim 15, wherein reducing the number of ports in the memory array comprises:

responsive to a determination that the memory array is a write-before-read array, identifying a read port and a write port, wherein the write port address matches the read port and every time the read port is enabled, the write port is also enabled; and

for each connected write pin, merging a corresponding read pin onto the connected write pin.

21. The computer program product of claim 15, wherein the computer readable program is stored in a computer readable storage medium in a data processing system and wherein the computer readable program was downloaded over a network from a remote data processing system.

22. The computer program product of claim 15, wherein the computer readable program is stored in a computer readable storage medium in a server data processing system and wherein the computer readable program is downloaded over a network to a remote data processing system for use in a computer readable storage medium with the remote system.

23. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to;

receive an integrated circuit design having a memory array;

reduce a number of ports in the memory array in the integrated circuit design to form a reduced integrated circuit design; and

perform synthesis or verification on the reduced integrated circuit design.