POWER SEMICONDUCTOR STRUCTURE WITH FIELD EFFECT RECTIFIER AND FABRICATION METHOD THEREOF

• US 20110278642A1
• Filed: 04/07/2011
• Published: 11/17/2011
• Est. Priority Date: 05/13/2010
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Great Power Semiconductor Corp.
• Inventors: TU, KAO-WAY
• Granted Patent: US 8,357,952 B2
• Time in Patent Office: Days
• US Class Current: 257/130
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Claims

1. A power semiconductor structure with a field effect rectifier, comprising:

a drain region;

a body region, located above the drain region;

a source region, located in the body region;

a gate channel, located in the body region and adjacent to a gate structure; and

a current channel, located in the body region and adjacent to a conductive structure coupled to the source region, the current channel being extended from the source region downward to the drain region, and the current channel is much shorter than the gate channel.

2. The power semiconductor structure with a field effect rectifier of claim 1, wherein the conductive structure is located in a trench extended downward from the source region.

3. The power semiconductor structure with a field effect rectifier of claim 1, wherein the gate channel is extended downward from the source region to the drain region.

4. The power semiconductor structure with a field effect rectifier of claim 3, wherein the gate channel and the current channel are located on the opposite sides of the body region, and a first thickness of the body region with respect to the current channel is smaller than a second thickness of the body region with respect to the gate channel.

5. The power semiconductor structure with a field effect rectifier of claim 4, wherein a first depth of the body region with respect to the current channel is smaller than a second depth of the body region with respect to the gate channel.

6. The power semiconductor structure with a field effect rectifier of claim 4, wherein the body region has a hollow area on an upper surface thereof respective to the conductive structure.

7. A fabrication method of a power semiconductor structure with a field effect rectifier comprising the steps of:

(a) providing a base with a drain region therein;

(b) forming a conductive structure above the drain region;

(c) forming a body region surrounding the conductive structure; and

(d) forming a source region in the body region to form a current channel in the body region adjacent to the conductive structure extended downward from the source region to the drain region.

8. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 7, further comprising the steps of forming a source metal layer electrically connecting the source region and the conductive structure.

9. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 7, wherein at least a gate structure is formed in the substrate during the step of forming the conductive structure.

10. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 7, after the formation of the body region, further comprising the step of forming a hollow area on an upper surface of the body region respective to the conductive structure to have a first thickness of the body region with respect to the current channel being smaller than a second thickness of the body region with respect to the gate channel.

11. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 7, wherein the conductive structure has a horizontal portion, the step of forming the body region is to implant dopants into the base by using the conductive structure as a mask so as to have a first thickness of the body region with respect to the current channel being smaller than a second thickness of the body region with respect to the gate channel.

12. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 7, wherein the step of forming the conductive structure comprises:

forming at least two trenches in the base;

forming a dielectric layer lining the inner surface of the trenches; and

forming the conductive structure and the gate structure in the trenches respectively.

13. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 12, wherein the step of forming at least two trenches in the base comprises:

forming at least a first trench and at least a second trench in the base by using an first lithographic and etching step; and

widening an upper portion of the second trench by using a second lithographic and etching step;

wherein the first trench is utilized for locating the gate structure and the second trench is utilized for locating the conductive structure, and the current channel is located on a side surface of a lower portion of the second trench.

14. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 13, wherein the step of forming the source region above the body region comprises:

forming a first source region on the side surface of the lower portion of the second trench; and

forming a second source region in a surface layer of the body region between the first trench and the second trench.

15. The fabrication method of a power semiconductor structure with a field effect rectifier of claim 14, further comprising the step of implanting dopants to the side surface of the widened upper portion of the second trench with a tilted angle.