Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die

• US 20110278707A1
• Filed: 05/17/2010
• Published: 11/17/2011
• Est. Priority Date: 05/17/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Park, YeongIm, Lee, HyungMin, Chi, HeeJo
• Granted Patent: US 8,357,564 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2221/68386 Separation by peeling
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16245 : the item being metallic
• CPC Class Codes: H01L 2224/21 : of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2105 : Shape
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/22 : of a plurality of HDI interconnects
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48105 : Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/48175 : the item being metallic
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 : the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49517 : Additional leads
• CPC Class Codes: H01L 23/49527 : the additional leads being a multilayer
• CPC Class Codes: H01L 23/49537 : Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias.

Claims

1. A method of making a semiconductor device, comprising:

providing a first temporary carrier;

mounting a prefabricated multi-die leadframe having a plurality of contact pads over the first temporary carrier;

mounting a first semiconductor die over the first temporary carrier between the contact pads of the leadframe;

mounting a second semiconductor die over the contact pads of the leadframe and over the first semiconductor die;

depositing an encapsulant over the leadframe and first and second semiconductor die;

removing the first temporary carrier;

forming a first interconnect structure over the leadframe and the first semiconductor die and a first surface of the encapsulant; and

cutting a channel through the encapsulant and leadframe to separate the contact pads of the leadframe.

2. The method of claim 1, further including:

mounting a second temporary carrier to a second surface of the encapsulant opposite the first surface of the encapsulant; and

removing the second temporary carrier after cutting the channel through the encapsulant and leadframe.

3. The method of claim 1, further including removing a portion of the encapsulant to expose a surface of the second semiconductor die.

4. The method of claim 1, further including:

forming a plurality of vias through the encapsulant; and

filling the vias with conductive material to form conductive vias.

5. The method of claim 4, further including forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant, the second interconnect structure being electrically connected to the conductive vias.

6. The method of claim 4, further including:

providing a second leadframe having a base and plurality of contact pads;

mounting the second leadframe over a second surface of the encapsulant opposite the first surface of the encapsulant, the contact pads of the second leadframe being electrically connected to the conductive vias; and

removing the base of the second leadframe to separate the contact pads of the second leadframe.

7. The method of claim 1, further including forming a bond wire between the second semiconductor die and a contact pad of the leadframe.

8. A method of making a semiconductor device, comprising:

providing a first carrier;

mounting a multi-die leadframe having a plurality of contact pads over the first carrier;

mounting a first semiconductor die over the first carrier between the contact pads of the leadframe;

mounting a second semiconductor die over the contact pads of the leadframe and over the first semiconductor die;

depositing an encapsulant over the leadframe and first and second semiconductor die;

removing the first carrier; and

forming a first interconnect structure over the leadframe and the first semiconductor die and a first surface of the encapsulant.

9. The method of claim 8, further including cutting a channel through the encapsulant and leadframe to separate the contact pads of the leadframe.

10. The method of claim 9, further including:

mounting a second carrier to a second surface of the encapsulant opposite the first surface of the encapsulant; and

removing the second carrier after cutting the channel through the encapsulant and leadframe.

11. The method of claim 8, further including forming a plurality of conductive vias through the encapsulant.

12. The method of claim 11, further including forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant, the second interconnect structure being electrically connected to the conductive vias.

13. The method of claim 11, further including:

providing a second leadframe having a base and plurality of contact pads;

mounting the second leadframe over a second surface of the encapsulant opposite the first surface of the encapsulant, the contact pads of the second leadframe being electrically connected to the conductive vias; and

removing the base of the second leadframe to separate the contact pads of the second leadframe.

14. A method of making a semiconductor device, comprising:

providing a multi-die leadframe having a plurality of contact pads;

mounting a first semiconductor die between the contact pads of the leadframe;

mounting a second semiconductor die over the contact pads of the leadframe and over the first semiconductor die;

depositing an encapsulant over the leadframe and first and second semiconductor die; and

forming a first interconnect structure over the leadframe and the first semiconductor die and a first surface of the encapsulant.

15. The method of claim 14, further including:

providing a first carrier;

mounting the multi-die leadframe over the first carrier; and

removing the first carrier after depositing the encapsulant.

16. The method of claim 15, further including cutting a channel through the encapsulant and leadframe to separate the contact pads of the leadframe.

17. The method of claim 16, further including:

mounting a second carrier to a second surface of the encapsulant opposite the first surface of the encapsulant; and

removing the second carrier after cutting the channel through the encapsulant and leadframe.

18. The method of claim 14, further including forming a plurality of conductive vias through the encapsulant.

19. The method of claim 18, further including forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant, the second interconnect structure being electrically connected to the conductive vias.

20. The method of claim 18, further including:

providing a second leadframe having a base and plurality of contact pads;

mounting the second leadframe over a second surface of the encapsulant opposite the first surface of the encapsulant, the contact pads of the second leadframe being electrically connected to the conductive vias; and

removing the base of the second leadframe to separate the contact pads of the second leadframe.

21. A semiconductor device, comprising:

a multi-die leadframe having a plurality of contact pads;

a first semiconductor die mounted between the contact pads of the leadframe;

a second semiconductor die mounted over the contact pads of the leadframe and over the first semiconductor die;

an encapsulant deposited over the leadframe and first and second semiconductor die; and

a first interconnect structure formed over the leadframe and the first semiconductor die and a first surface of the encapsulant.

22. The semiconductor device of claim 21, further including a plurality of conductive vias formed through the encapsulant.

23. The semiconductor device of claim 22, further including a second interconnect structure formed over a second surface of the encapsulant opposite the first surface of the encapsulant, the second interconnect structure being electrically connected to the conductive vias.

24. The semiconductor device of claim 21, wherein a portion of the encapsulant is removed to expose a surface of the second semiconductor die.

25. The semiconductor device of claim 21, further including a bond wire formed between the second semiconductor die and a contact pad of the leadframe.