Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

• US 20110278736A1
• Filed: 07/26/2011
• Published: 11/17/2011
• Est. Priority Date: 12/12/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Chen, Kang, Lin, Yaojian
• Granted Patent: US 9,082,806 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03003 for holding or transferring a preform
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0613 Square or rectangular array
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13015 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14104 : relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16111 : the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06544 : Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/04 : Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.

Claims

1. A method of making a semiconductor device, comprising:

providing a temporary carrier;

mounting a semiconductor die with an active surface oriented toward the temporary carrier;

depositing an encapsulant with a first surface over the temporary carrier and a second surface opposite the first surface, the second surface being over a backside of the semiconductor die;

removing the temporary carrier;

removing a portion of the encapsulant in a periphery of the semiconductor die to form an opening in the first surface of the encapsulant;

forming an interconnect structure over the active surface of the semiconductor die and extending into the opening;

forming a via from the second surface of the encapsulant to the opening; and

forming a first bump in the via that electrically connects to the interconnect structure.

2. The method of claim 1, wherein the second surface of the encapsulant includes a step with a vertical offset.

3. The method of claim 1, further including depositing a temporary planarization and protection layer over the active surface of the semiconductor die.

4. The method of claim 1, further including depositing a crack stop layer over the active surface of the semiconductor die.

5. The method of claim 1, wherein forming the interconnect structure includes:

depositing a first insulation layer over the active surface of the semiconductor die and over the first surface of the encapsulant;

depositing a conductive layer over the first insulation layer, the conductive layer being electrically connected to the first bump;

depositing a second insulation layer over the conductive layer; and

forming a second bump over the second insulation layer and electrically connected to the conductive layer.

6. The method of claim 1, further including forming a plurality of vias organized as an array with multiple rows wherein the plurality of vias extends from the second surface of the encapsulant to openings in the first surface of the encapsulant.

7. The method of claim 1, further including depositing back grinding tape over the interconnect structure before forming the first bump in the via.

8. A method of making a semiconductor device, comprising:

providing a semiconductor die with an active surface;

depositing an encapsulant in a periphery of the semiconductor die with a first surface and a second surface opposite the first surface and over a backside of the semiconductor die;

removing a portion of the encapsulant from the first surface to form an opening;

forming an interconnect structure over the active surface of the semiconductor die and extending into the opening;

forming a via from the second surface of the encapsulant to the opening; and

depositing a conductive material in the via that electrically connects to the interconnect structure.

9. The method of claim 8, further including mounting a backside alignment unit in the periphery of the semiconductor die.

10. The method of claim 8, further including forming the opening by laser drilling, wherein a sidewall of the via includes a vertical or tapered profile.

11. The method of claim 8, further including mounting the interconnect structure over a reusable carrier before depositing the conductive material into the via.

12. The method of claim 8, wherein the interconnect structure includes:

depositing a first insulation layer over the active surface of the semiconductor die and over the first surface of the encapsulant;

depositing a conductive layer over the first insulation layer, the conductive layer being electrically connected to the conductive material;

depositing a second insulation layer over the conductive layer; and

forming a copper pillar over the second insulation layer and electrically connected to the conductive layer.

13. The method of claim 8, further including mounting a semiconductor package over the semiconductor die and electrically connected to the interconnect structure through the conductive material in the via.

14. The method of claim 8, further including removing a portion of the encapsulant to expose the backside of the semiconductor die.

15. The method of claim 14, further including forming a heat sink or shielding layer over the backside of the semiconductor die.

16. A method of making a semiconductor device, comprising:

providing a semiconductor die with an active surface;

depositing an encapsulant in a periphery of the semiconductor die with a first surface and a second surface opposite the first surface;

depositing a conductive material in the periphery of the semiconductor die extending from the first surface to the second surface of the encapsulant; and

forming an interconnect structure over the active surface of the semiconductor die and electrically connected to the conductive material.

17. The method of claim 16, wherein depositing the conductive material includes forming a copper pillar.

18. The method of claim 16, wherein the second surface of the encapsulant includes a step with a vertical offset.

19. The method of claim 16, further including depositing a temporary planarization and protection layer over the active surface of the semiconductor die.

20. The method of claim 16, further including depositing back grinding tape over the interconnect structure before depositing a conductive material in the periphery of the semiconductor die.

21. A semiconductor device, comprising:

a semiconductor die with an active surface;

an encapsulant deposited in a periphery of the semiconductor die with a first surface and a second surface opposite the first surface;

an interconnect structure formed over the active surface of the semiconductor die; and

a conductive via that extends from the second surface of the encapsulant to the interconnect structure.

22. The semiconductor device of claim 21, wherein the conductive via that extends from the second surface of the encapsulant to the interconnect structure includes a sidewall with a vertical or tapered profile.

23. The semiconductor device of claim 21, further including a crack stop layer deposited over the active surface of the semiconductor die.

24. The semiconductor device of claim 21, further including a backside alignment unit mounted in the periphery of the semiconductor die.

25. The semiconductor device of claim 21, further including a plurality of conductive vias that extend from the second surface to the first surface of the encapsulant and are organized as an array with multiple rows.