METHOD, ELECTRIC CIRCUIT ARRANGEMENT AND ELECTRIC MEMORY UNIT FOR DETERMINING A CHARACTERISTIC STATUS PARAMETER OF THE MEMORY UNIT

• US 20110279122A1
• Filed: 01/14/2010
• Published: 11/17/2011
• Est. Priority Date: 01/28/2009
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Butzmann, Stefan
• Granted Patent: US 8,797,040 B2
• Time in Patent Office: Days
• US Class Current: 324/426
• CPC Class Codes: G01R 31/382 Arrangements for monitoring battery or accumulator variables, e.g. SoC
• CPC Class Codes: G01R 31/389 Measuring internal impedance, internal conductance or related variables
• CPC Class Codes: G01R 31/392 Determining battery ageing or deterioration, e.g. state of health
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

The invention relates to a method for determining a characteristic status parameter of a memory unit via an electric circuit arrangement. In the circuit arrangement at least one inductive component and at least one capacitive component are arranged, forming a tuned circuit with the memory unit. The method has the following steps of energizing the tend circuit by temporary charging of the capacitive component, the energizing being carried out by an energizing device electrically supplied by the memory unit, and determining a time-dependent voltage change at the capacitive component after terminating the energizing and determining the characteristic status parameter from the time-dependence of the voltage change. The invention further relates to a corresponding electrical circuit arrangement and an electrical memory, including such a circuit arrangement.

Claims

1-11. -11. (canceled)

12. A method for determining a characteristic status parameter of a memory unit by means of an electric circuit arrangement in which at least one inductive component and at least one capacitive component, which with the memory unit form an oscillator circuit, are disposed, having the following steps:

exciting the oscillator circuit by temporary subjection of the capacitive component to a charge, the exciting being effected by an excitation device supplied electrically by the memory unit;

ascertaining a time-dependent voltage change at the capacitive component after termination of the excitation; and

determining the characteristic status parameter from a time dependency of the voltage change.

13. The method as defined by claim 12, wherein the characteristic status parameter is a state of charge and/or an aging status and/or a state of health of the memory unit.

14. The method as defined by claim 12, wherein at least one further capacitive component of the circuit arrangement is connected in, and for determining the parameter from a changed time-dependent voltage change, the oscillator circuit is re-excited.

15. The method as defined by claim 13, wherein at least one further capacitive component of the circuit arrangement is connected in, and for determining the parameter from a changed time-dependent voltage change, the oscillator circuit is re-excited.

16. The method as defined by claim 12, wherein the oscillator circuit, after the time-dependent voltage change is ascertained, is damped by connecting in at least one electrical resistor having a resistance value higher than an internal resistance of the memory unit.

17. The method as defined by claim 15, wherein the oscillator circuit, after the time-dependent voltage change is ascertained, is damped by connecting in at least one electrical resistor having a resistance value higher than an internal resistance of the memory unit.

18. The method as defined by claim 12, wherein the excitation device has another inductive component, which by means of a short-circuit current builds up a magnetic field, which magnetic field, after the shutoff of the short-circuit current, generates a current flow which temporarily subjects the capacitive component to a charge.

19. The method as defined by claim 17, wherein the excitation device has another inductive component, which by means of a short-circuit current builds up a magnetic field, which magnetic field, after the shutoff of the short-circuit current, generates a current flow which temporarily subjects the capacitive component to a charge.

20. An electric circuit arrangement for determining a characteristic status parameter of an electric memory unit that is dependent on an internal resistance of the memory unit, for performing a method as defined by claim 12, having a current path, which has an inductive component and a capacitive component connected in series and which is electrically connected by two connection lines to the memory unit thereby forming an oscillator circuit, and having an excitation device, supplied electrically by the memory unit, which excitation device, for exciting the oscillator circuit, is interconnected with the capacitive component by a temporary subjection of that capacitive component to a charge.

21. An electric circuit arrangement for determining a characteristic status parameter of an electric memory unit that is dependent on an internal resistance of the memory unit, for performing a method as defined by claim 19, having a current path, which has an inductive component and a capacitive component connected in series and which is electrically connected by two connection lines to the memory unit thereby forming an oscillator circuit, and having an excitation device, supplied electrically by the memory unit, which excitation device, for exciting the oscillator circuit, is interconnected with the capacitive component by a temporary subjection of that capacitive component to a charge.

22. The circuit arrangement as defined by claim 20, wherein the excitation device has a short-circuit current path with a switch, which short-circuit current path is connected parallel to the capacitive component via excitation lines, and the excitation device is also connected to the memory unit via supply lines, and one of the excitation lines has a diode, and a supply line connected to this excitation line has a further inductive component.

23. The circuit arrangement as defined by claim 21, wherein the excitation device has a short-circuit current path with a switch, which short-circuit current path is connected parallel to the capacitive component via excitation lines, and the excitation device is also connected to the memory unit via supply lines, and one of the excitation lines has a diode, and a supply line connected to this excitation line has a further inductive component.

24. The circuit arrangement as defined by claim 20, having at least one further current path, which is connected parallel to the capacitive component and has a further capacitive component and a further switch connected in series.

25. The circuit arrangement as defined by claim 22, having at least one further current path, which is connected parallel to the capacitive component and has a further capacitive component and a further switch connected in series.

26. The circuit arrangement as defined by claim 23, having at least one further current path, which is connected parallel to the capacitive component and has a further capacitive component and a further switch connected in series.

27. The circuit arrangement as defined by claim 20, having at least one damping current path, which is connected parallel to the inductive component and has a resistor element, having a resistance value higher than the internal resistance, and a switch connected in series.

28. The circuit arrangement as defined by claim 26, having at least one damping current path, which is connected parallel to the inductive component and has a resistor element, having a resistance value higher than the internal resistance, and a switch connected in series.

29. The circuit arrangement as defined by claim 20, having a measuring instrument, which for ascertaining a time-dependent voltage change at the capacitive component is interconnected with that capacitive component.

30. The circuit arrangement as defined by claim 28, having a measuring instrument, which for ascertaining a time-dependent voltage change at the capacitive component is interconnected with that capacitive component.

31. An electric memory, in particular an electric memory of an electric drive and/or hybrid drive of a motor vehicle, having at least one electric memory unit and having at least one circuit arrangement as defined by claim 20.