IMAGER ARRAY INTERFACES

• US 20110279721A1
• Filed: 05/12/2011
• Published: 11/17/2011
• Est. Priority Date: 05/12/2010
• Status: Active Grant

• Current Assignee: FotoNation Limited (Adeia Inc.)
• Original Assignee: Pelican Imaging Corporation
• Inventors: McMahon, Andrew Kenneth John
• Granted Patent: US 8,928,793 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H04N 23/13 with multiple sensors
• CPC Class Codes: H04N 23/951 by using two or more images to influence resolution, frame rate or aspect ratio
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
• CPC Class Codes: H04N 25/44 by partially reading an SSIS array
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image
• CPC Class Codes: H04N 25/704 Pixels specially adapted for focusing, e.g. phase difference pixel sets
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Architectures for imager arrays configured for use in array cameras in accordance with embodiments of the invention are described. One embodiment of the invention includes a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane, control circuitry configured to control the capture of image information by the pixels within the focal planes, where the control circuitry is configured so that the capture of image information by the pixels in at least two of the focal planes is separately controllable, sampling circuitry configured to convert pixel outputs into digital pixel data, and output interface circuitry configured to transmit pixel data via an output interface.

Claims

1. An imager array, comprising:

a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane;

control circuitry configured to control the capture of image information by the pixels within the focal planes, where the control circuitry is configured so that the capture of image information by the pixels in at least two of the focal planes is separately controllable;

sampling circuitry configured to convert pixel outputs into digital pixel data; and

output interface circuitry configured to transmit pixel data via an output interface.

2. The imager array of claim 1, wherein:

the imager array includes M×

N focal planes;

the output interface includes less than M×

N output ports; and

the control circuitry is configured to time multiplex the pixel data onto the output ports of the output interface.

3. The imager array of claim 1, wherein the control circuitry further comprises memory configured to buffer pixel data from the plurality of focal planes until a time-slot is available on an output port of the output interface to transmit the pixel data.

4. The imager array of claim 1, wherein the control circuitry is configured to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying a focal plane.

5. The imager array of claim 1, wherein the control circuitry is configured to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying at least one row of pixels within a focal plane.

6. The imager array of claim 1, wherein the control circuitry is configured to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying at least one column of pixels within a focal plane.

7. The imager array of claim 1, wherein the control circuitry is configured to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying the relative time of pixel data capture.

8. The imager array of claim 7, wherein the codes provide information identifying the relative start time of the pixel data capture.

9. The imager array of claim 7, wherein the codes provide information identifying the relative end time of the pixel data capture.

10. The imager array of claim 7, wherein the control circuitry further comprises a counter and the codes that provide information identifying the relative time of pixel data capture are generated using the counter.

11. The imager array of claim 1, wherein the control circuitry is configured to insert codes between the pixel data transmitted via the output interface, where the codes provide information concerning operating parameters of the imager array.

12. The imager array of claim 11, wherein the codes provide the integration time of each focal plane.

13. The imager array of claim 11, wherein the codes provide the gain of each focal plane.

14. The imager array of claim 1, wherein the output interface circuitry is configured to insert a frame blanking interval between transmission of pixel data via the output interface.

15. The imager array of claim 14, wherein the output interface circuitry is further configured to insert a line blanking interval between transmission of lines of pixel data via the output interface.

16. The imager array of claim 1, wherein the output interface circuitry is configured to transform the pixel data by performing bit reductions.

17. A method of obtaining pixel data, comprising:

separately capturing pixel data using an imager array having a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane;

during the capture of the pixel data, buffering portions of the captured pixel data within memory in the imager array; and

transmitting the buffered pixel data via an output interface in the imager array when a time-slot is available on an output port.

18. The method of claim 17, further comprising using control circuitry on the imager array to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying a focal plane.

19. The method of claim 17, further comprising using control circuitry on the imager array to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying at least one row of pixels within a focal plane.

20. The method of claim 17, further comprising using control circuitry on the imager array to insert codes between the pixel data transmitted via the output interface, where the codes provide information identifying at least one of:

at least one column of pixels within a focal plane;

the relative time of pixel data capture;

the relative start time of the pixel data capture;

the relative end time of the pixel data capture;

the integration time of each focal plane; and

the gain of each focal plane.

21. The method of claim 17, further comprising using control circuitry on the imager array to insert a line blanking interval between transmissions of buffered pixel data via the output interface.

22. The method of claim 20, further comprising using control circuitry on the imager array to insert a frame blanking interval upon completion of the transmission of the captured pixel data.