SYNCHRONIZATION OF A GENERATED CLOCK
First Claim
Patent Images
1. A circuit comprising:
- an oscillator circuit configured to provide an internal oscillator signal, the internal oscillator signal comprising internal reference pulse edges substantially at an internal reference frequency;
a frequency counter configured to receive an external reference signal that comprises periodic pulse edges and the internal oscillator signal, the frequency counter further configured to output a count value that represents a number of internal reference pulse edges counted between two external reference signal periodic pulse edges;
a correction signal generator configured to receive the count value, the correction signal generator outputs an oscillator fast signal when the count value is equal to a predetermined first number and outputs an oscillator slow signal when the count value is equal to a predetermined second number, the predetermined first number being greater than the predetermined second number;
a variable divide-by circuit configured to receive the oscillator fast signal, the oscillator slow signal and the internal oscillator signal, the variable divide-by circuit is configured to provide a conditioned output having an output frequency equal to the internal reference frequency divided by a first number when in receipt of the oscillator fast signal, equal to the internal reference frequency divided by a second number when in receipt of the oscillator slow signal, or equal to the internal oscillator reference frequency divided by a third number.
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Abstract
A real time clock circuit is provided that has an onboard oscillator continuously providing an internal clock frequency, which is digitally synchronized to a more accurate reference clock frequency. An exemplary real time clock inhibits synchronization of the internal clock frequency when the reference clock is unavailable or if the reference clock'"'"'s frequency is outside of a defined accuracy range.
29 Citations
20 Claims
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1. A circuit comprising:
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an oscillator circuit configured to provide an internal oscillator signal, the internal oscillator signal comprising internal reference pulse edges substantially at an internal reference frequency; a frequency counter configured to receive an external reference signal that comprises periodic pulse edges and the internal oscillator signal, the frequency counter further configured to output a count value that represents a number of internal reference pulse edges counted between two external reference signal periodic pulse edges; a correction signal generator configured to receive the count value, the correction signal generator outputs an oscillator fast signal when the count value is equal to a predetermined first number and outputs an oscillator slow signal when the count value is equal to a predetermined second number, the predetermined first number being greater than the predetermined second number; a variable divide-by circuit configured to receive the oscillator fast signal, the oscillator slow signal and the internal oscillator signal, the variable divide-by circuit is configured to provide a conditioned output having an output frequency equal to the internal reference frequency divided by a first number when in receipt of the oscillator fast signal, equal to the internal reference frequency divided by a second number when in receipt of the oscillator slow signal, or equal to the internal oscillator reference frequency divided by a third number. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A real-time clock circuit comprising:
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an external clock input adapted to receive an external clock signal; a divider circuit connected to receive the external clock signal and output an external reference signal comprising an external reference signal frequency of a desired accuracy; an internal reference signal line connected to provide an internal reference signal having an internal reference signal frequency that is less accurate over time than the desired accuracy, the internal reference signal frequency being higher than the external reference signal frequency; and a synchronization circuit comprising a variable divide-by circuit, wherein during each cycle of the external reference signal, the variable divide-by circuit divides the internal reference signal frequency by a count value to produce a conditioned output signal having a conditioned frequency that over time is substantially as accurate as the desired accuracy, the count value being the number of internal reference signal pulses within one cycle of the external reference signal; and
wherein the variable divide-by circuit produces the conditioned output signal by dividing the internal reference signal frequency by a fixed number when the external clock signal is not available. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A real-time clock circuit comprising:
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an oscillation circuit adapted to produce an oscillation signal having an oscillation frequency; a divide down circuit adapted to receive the oscillation signal and to divide the oscillation signal down and to provide an internal reference signal having an internal reference signal frequency; a divide circuit adapted to receive an external signal having an external signal oscillation frequency of a desired accuracy, the divide circuit further adapted to divide the external signal oscillation frequency by a selectable number and provide an external reference signal having an external reference frequency, the internal reference signal frequency being less accurate over time than the external reference frequency; a synchronization circuit adapted to receive both the internal reference signal and the external reference signal, the synchronization circuit counts a count value that equals a number of internal reference signal pulse edges that are within an external reference signal cycle and uses the count value to adjust a divisor of a variable divide-by circuit to produce a corrected output signal, the corrected output signal comprising a corrected output frequency that is substantially as accurate as the desired accuracy. - View Dependent Claims (19, 20)
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Specification