SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20110281426A1
• Filed: 05/13/2011
• Published: 11/17/2011
• Est. Priority Date: 05/14/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Joon Goo, Kim, Myeongcheol, Kim, Dohyoung, Kim, Yoonhae, Lee, Jin Wook, Jeong, Sooyeon, Kim, Yongjin
• Granted Patent: US 8,716,117 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

Claims

1. A method of forming a semiconductor device, comprising:

forming gate electrodes on a semiconductor substrate and forming spacers on first and second side surfaces of the gate electrodes;

forming capping patterns on the gate electrodes; and

forming a metal contact between the gate electrodes,

wherein each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

2. The method of claim 1, wherein forming gate electrodes and forming spacers comprises:

forming dummy gate patterns on the semiconductor substrate;

forming the spacers on side surfaces of the dummy gate patterns; and

removing the dummy gate patterns to form a first opening,

wherein the gate electrodes are formed in the first opening.

3. The method of claim 2, further comprising, prior to forming the gate electrodes, forming a gate insulating layer in the first opening.

4. The method of claim 2, wherein, after the gate electrodes are formed, upper surfaces of the gate electrodes are exposed, and lower surfaces of the capping patterns contact the upper surfaces of the gate electrodes.

5. The method of claim 1, wherein a side surface of the capping pattern is horizontally offset with respect to at least one of the first and second side surfaces of each of the gate electrodes.

6. The method of claim 1, wherein the capping patterns are formed to cover the gate electrodes and at least some of the spacers.

7. The method of claim 1, wherein forming the capping patterns comprises:

forming a first insulating layer disposed between the spacers;

forming a second insulating layer covering the first insulating layer and the gate electrodes; and

forming first mask patterns having second openings on the second insulating layer,

wherein the first mask patterns are formed with a width greater than the width of the gate electrodes.

8. The method of claim 7, wherein the width of each of the first mask patterns is greater than or equal to a sum of the width of each of the gate electrodes and widths of the spacers on both side surfaces of each of the gate electrodes.

9. The method of claim 7, wherein forming the capping patterns comprises forming second mask patterns on the first mask patterns, the second mask patterns having third openings, the third openings being greater in width than the second openings and exposing the second openings,

wherein the second openings are formed in a line shape and the third openings are formed in a hole or bar shape.

10. The method of claim 9, wherein forming the capping patterns further comprises, after forming the first mask patterns, forming a third insulating layer filling the second opening.

11. The method of claim 9, wherein forming the capping patterns further comprises etching the second insulating layer using the first and second mask patterns as a mask.

12. The method of claim 11, wherein etching the second insulating layer comprises etching the first insulating layer and the third insulating layer.

13. The method of claim 12, further comprising, after etching the first, second and third insulating layers, removing the second mask patterns and forming a subsidiary insulating layer covering the first mask patterns, the capping patterns and the spacers.

14. The method of claim 13, further comprising etching some of the first mask patterns and the subsidiary insulating layer to expose an upper surface of the semiconductor substrate.

15. The method of claim 14, further comprising, prior to forming the first insulating layer, forming an etch stopper layer covering the spacers and the semiconductor substrate.

16. The method of claim 15, wherein exposing the semiconductor substrate comprises etching the etch stopper layer covering the semiconductor substrate to form an etch stopper pattern on the spacers.

17. The method of claim 14, further comprising forming a silicide layer on the exposed semiconductor substrate, wherein the metal contacts are formed on the silicide layer.

18. The method of claim 17, wherein forming the metal contact comprises forming a metal layer filling a space between the gate electrodes, and recessing some of the metal layer and the first mask patterns to expose the capping patterns.

19. The method of claim 1, wherein the gate electrode comprises at least one of a metal and a metal compound.

20. The method of claim 1, wherein the capping pattern comprises a silicon oxide layer.

21. The method of claim 1, wherein the gate electrode comprises at least one of aluminum, titanium nitride and tantalum nitride.

22. The method of claim 7, wherein:

forming the capping patterns further comprises forming second mask patterns on the first mask patterns, the second mask patterns having third openings, the third openings being greater in width than the second openings and exposing the second openings;

the second openings are formed in a line shape and the third openings are formed in a hole or bar shape, and

the third openings comprise an extending opening which exposes the second openings adjacent to each other at the same time.

23. The method of claim 22, wherein forming the capping patterns comprises etching at least some of the first mask pattern exposed by the extending opening to form a recess pattern.

24. The method of claim 23, wherein forming the metal contacts comprises forming a metal layer filling a space between the gate electrodes and etching some of the metal layer to expose at least one of the first mask patterns.

25. The method of claim 24, wherein the metal contacts are connected to each other on the recess pattern.

26. A method of forming a semiconductor device, comprising:

forming a dummy gate pattern on a semiconductor substrate;

forming a spacer on a sidewall of the dummy gate pattern;

forming an etch stopper layer covering the dummy gate pattern and the spacer;

forming a first insulating layer on the etch stopper layer;

performing a planarizing process for the first insulating layer and the etch stopper layer to expose an upper surface of the dummy gate pattern;

removing the dummy gate pattern;

forming gate electrodes on a region from which the dummy gate pattern is removed;

forming capping patterns on the gate electrodes; and

forming a metal contact between the gate electrodes,

wherein each of the capping patterns is formed with a width which is greater than a width of the gate electrodes.

27. The method of claim 26, further comprising, prior to forming the dummy gate pattern on the semiconductor substrate, forming a sacrificial oxide layer on the semiconductor substrate.

28. The method of claim 27, further comprising, after removing the dummy gate pattern, removing the sacrificial oxide layer such that the semiconductor substrate is exposed.

29. The method of claim 28, further comprising, prior to forming the gate electrode, forming a gate insulating layer on the exposed semiconductor substrate.

30-42. -42. (canceled)

43. A method of forming a semiconductor device, comprising:

forming a sacrificial oxide layer on a semiconductor substrate;

forming a dummy gate pattern on the sacrificial oxide layer;

forming a spacer on a sidewall of the dummy gate pattern;

forming an etch stopper layer covering the dummy gate pattern and the spacer;

forming a first insulating layer on the etch stopper layer;

performing a planarizing process for the first insulating layer and the etch stopper layer to expose an upper surface of the dummy gate pattern;

removing the dummy gate pattern;

removing the sacrificial oxide layer such that the semiconductor substrate is exposed;

forming a gate insulating layer on the exposed semiconductor substrate;

forming gate electrodes on a region from which the dummy gate pattern is removed;

forming capping patterns on the gate electrodes, wherein forming the capping patterns comprises;

forming a second insulating layer disposed between the spacers;

forming a third insulating layer covering the second insulating layer and the gate electrodes; and

forming first mask patterns having second openings on the third insulating layer, wherein the first mask patterns are formed with a width greater than the width of the gate electrodes, such that each of the capping patterns is formed with a width which is greater than a width of the gate electrodes; and

forming a metal contact between the gate electrodes.

44. The method of claim 43, wherein the width of each of the first mask patterns is greater than or equal to a sum of the width of each of the gate electrodes and widths of the spacers on both side surfaces of each of the gate electrodes.

45. The method of claim 43, further comprising forming second mask patterns on the first mask patterns, the second mask patterns having third openings being greater in width than the second openings.

46. The method of claim 43, further comprising forming a silicide layer on the exposed semiconductor substrate, wherein the metal contact is formed on the silicide layer.

47. The method of claim 43, wherein the gate electrode comprises at least one of a metal and a metal compound.

48. The method of claim 43, wherein the capping pattern comprises a silicon oxide layer.

49. The method of claim 43, wherein the gate electrode comprises at least one of aluminum, titanium nitride and tantalum nitride.

50. The method of claim 43, wherein forming the metal contact comprises forming a metal layer filling a space between the gate electrodes and etching some of the metal layer.