IMPLEMENTING NETWORK MANAGER QUARANTINE MODE
First Claim
1. A method for implementing a network manager quarantine mode in an interconnect system, said method comprising:
- providing a plurality of paths defined by links connected between each source interconnect chip and each destination interconnect chip;
providing each said interconnect chip with a network manager, said network manager sending end-to-end (ETE) heartbeats on said plurality of paths through the interconnect system to each destination interconnect chip;
each said network manager maintaining a heartbeat table with a respective counter to track path status of each path through the interconnect system to each destination interconnect chip;
said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths for a second interconnect chip; and
said network manager of a first interconnect chip, responsive to said detected path status change to no working paths for said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each said paths from during said quarantine time interval.
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Abstract
A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval.
23 Citations
24 Claims
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1. A method for implementing a network manager quarantine mode in an interconnect system, said method comprising:
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providing a plurality of paths defined by links connected between each source interconnect chip and each destination interconnect chip; providing each said interconnect chip with a network manager, said network manager sending end-to-end (ETE) heartbeats on said plurality of paths through the interconnect system to each destination interconnect chip; each said network manager maintaining a heartbeat table with a respective counter to track path status of each path through the interconnect system to each destination interconnect chip; said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths for a second interconnect chip; and said network manager of a first interconnect chip, responsive to said detected path status change to no working paths for said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each said paths from during said quarantine time interval. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 10, 11)
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7. The method as recited in 3 includes identifying a good path responsive to a predefined count value of said respective up/down counter for said path.
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12. A circuit for implementing a network manager quarantine mode in an interconnect system, said circuit comprising:
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an interconnect chip including a network manager, said network manager sending end-to-end (ETE) heartbeats on a plurality of paths through the interconnect system to each destination interconnect chip;
said plurality of paths defined by links connected between said interconnect chip and each said destination interconnect chip;each said network manager maintaining a heartbeat table with a respective counter to track path status of each said path through the interconnect system to each destination interconnect chip; said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths to a second interconnect chip; and said network manager of a first interconnect chip, responsive to said detected path status change to no working paths to said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each said paths from during said quarantine time interval. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A multiple-path local rack interconnect system comprising:
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a plurality of interconnect chips including a source interconnect chip and a destination interconnect chip; a plurality of paths defined by serial links connected between each of said plurality of interconnect chips; said interconnect chips including a network manager, said network manager sending end-to-end (ETE) heartbeats on a plurality of paths through the interconnect system to each destination interconnect chip;
said plurality of paths defined by links connected between said interconnect chip and each said destination interconnect chip;each said network manager maintaining a heartbeat table with a respective counter to track path status of each said path through the interconnect system to each destination interconnect chip; said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths to a second interconnect chip; and said network manager of a first interconnect chip, responsive to said detected path status change to no working paths to said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each said paths from during said quarantine time interval. - View Dependent Claims (20)
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21. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
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a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing a network manager quarantine mode in an interconnect system, said circuit comprising; an interconnect chip including a network manager, said network manager sending end-to-end (ETE) heartbeats on a plurality of paths through the interconnect system to each destination interconnect chip;
said plurality of paths defined by links connected between said interconnect chip and each said destination interconnect chip;each said network manager maintaining a heartbeat table with a respective counter to track path status of each said path through the interconnect system to each destination interconnect chip; said network manager of a first interconnect chip detecting a path status change from at least one valid path to no working paths to a second interconnect chip; and said network manager of a first interconnect chip, responsive to said detected path status change to no working paths to said second interconnect chip, establishing a quarantine mode for a programmable quarantine time interval to prevent advertising good heartbeats for each said paths from during said quarantine time interval, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit. - View Dependent Claims (22, 23, 24)
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Specification