TECHNIQUES FOR ACCELERATING COMPUTATIONS USING FIELD PROGRAMMABLE GATE ARRAY PROCESSORS

• US 20110283059A1
• Filed: 05/10/2011
• Published: 11/17/2011
• Est. Priority Date: 05/11/2010
• Status: Abandoned Application

• Current Assignee: Progeniq Pte., Ltd.
• Original Assignee: Progeniq Pte., Ltd.
• Inventors: Govindarajan, Sundar, Nathan, Darran, Iyer, Vinod Ranganathan
• Application Number:
  US13/104,579
• Publication Number:
  US 20110283059A1
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/06 Ray-tracing

Abstract

Various embodiments are disclosed for accelerating computations using field programmable gate arrays (FPGA). Various tree traversal techniques, architectures, and hardware implementations are disclosed. Various disclosed embodiments comprise hybrid architectures comprising a central processing unit (CPU), a graphics processor unit (GPU), a field programmable gate array (FPGA), and variations or combinations thereof, to implement raytracing techniques. Additional disclosed embodiments comprise depth-breadth search tree tracing techniques, blocking tree branch traversal techniques to avoid data explosion, compact data structure representations for ray and node representations, and multiplexed processing of multiple rays in a programming element (PE) to leverage pipeline bubble.

Claims

1. A hybrid raytracing apparatus, comprising:

a configurable logic circuit programmable to implement a tree traversal algorithm;

an intersection processor configurable to implement a ray-triangle intersection algorithm, wherein the intersection processor is in data communication with the field programmable gate array; and

a central processor configurable to control the field programmable gate array and the intersection processor.

2. The hybrid raytracing apparatus of claim 1, wherein the intersection processor is a graphics processor.

3. The hybrid raytracing apparatus of claim 1, wherein the intersection processor is a field programmable gate array.

4. The hybrid raytracing apparatus of claim 1, wherein the intersection processor is a central processor.

5. The hybrid raytracing apparatus of claim 1, comprising:

a block random access memory configurable to store tree structure data in data communication with the logic circuit.

6. The hybrid raytracing apparatus of claim 5, comprising

a high speed static random access memory in data communication with the block random access memory, wherein the high speed static random access memory is configurable to provide the logic circuit with the tree structure data.

7. The hybrid raytracing apparatus of claim 1, wherein the logic circuit is configured with at least one tree traversal core comprising:

at least one floating point computational circuit;

at least one control logic circuit; and

at least one memory storage element;

wherein the elements are configured to carry out the tree traversal algorithm.

8. The hybrid raytracing apparatus of claim 1, further comprising at least one primary first-in-first-out memory storage element in data communication with the tree traversal cores.

9. The hybrid raytracing apparatus of claim 8, further comprising at least one secondary first-in-last-out memory storage element in data communication with the tree traversal cores.

10. The hybrid raytracing apparatus of claim 5 wherein the block random access memory is on-chip.

11. The hybrid raytracing apparatus of claim 5, wherein the block random access memory is off-chip.

12. The hybrid raytracing apparatus of claim 5, wherein the block random access memory comprises:

a first block random access memory locatable on-chip; and

a second block random access memory locatable off-chip.

13. A logic element for tree traversal comprising:

at least one processor core comprising;

a first input to receive a ray;

a second input to receive a node;

an intersecting block to determine if there is an intersection between the ray and the node, wherein the intersecting block is configured to output the node if the node is a leaf node, and wherein the intersecting block is configured to output at least one child node if the node is not a leaf node;

a primary memory storage unit configurable to store the at least one child node;

a secondary memory storage unit configurable to store the at least one child node; and

a decision logic circuit, configurable to determine whether a node should be stored in the primary storage unit or in the secondary storage unit.

14. The logic element of claim 13, further comprising an output stack configurable to receive at least one leaf node.

15. The logic element of claim 13, wherein the primary memory storage unit is a first-in-first-out storage register.

16. The logic element of claim 13, wherein the secondary memory storage unit is a first-in-last-out storage register.

17. The logic element of claim 13, wherein the intersecting block comprises:

at least one subtractor circuit;

at least one multiplier circuit; and

at least one comparator circuit, wherein the at least one subtractor, the at least one multiplier, and the at least one comparator are configurable to perform an intersection test.

18. The logic element of claim 13 further comprising a first-in-first-out storage register connected to the second input, wherein the first-in-first-out storage register is configurable to store at least one node.

19. The logic element of claim 13 further comprising a first-in-first-out storage register connected to the first input, wherein the first-in-first-out storage register is configurable to store at least one ray.

20. The logic element of claim 13 further comprising a third input configurable to receive node data from the primary storage device and secondary storage device.

21. A method for tree traversal, comprising:

receiving, by a logic circuit, at least one ray packet containing at least one ray;

receiving, by the logic circuit, at least one node of a k-dimensional (KD) tree;

traversing the KD tree, by the logic circuit, by performing an intersection test between the at least one ray and the at least one node;

wherein if the intersection test is positive, performing, via the logic circuit, a leaf node test, wherein if the leaf node test is positive a leaf node is output; and

wherein if the leaf node test is negative, calculating, by a floating point processor, two intersection intervals, wherein the intersection intervals are used by at least one child node of the at least one node for intersection tests, and wherein the at least one child node are output for continued tree traversal.

22. The method of claim 21, further comprising processing the at least one node in a depth breadth search algorithm.

23. The method of claim 21, further comprising performing the traversal of the KD tree by testing only a first ray and a second ray which define the outer bounds of a ray-beam.

24. The method of claim 23, further comprising performing, via the logic circuit, a ray-box intersection test.

25. The method of claim 24, further comprising performing the ray-box intersection test by simultaneously testing a single bounding box against at least one ray that comprise the ray-beam.

26. The method of claim 24, further comprising:

performing, via the logic circuit, an early-exit test using at least one bounding box obtained from the ray-box intersection test.