Maintenance Operations in a DRAM
1 Assignment
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Accused Products
Abstract
A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
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Citations
66 Claims
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1-33. -33. (canceled)
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34. A method of operating a memory controller in a system that includes the memory controller and a memory device, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:
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transmitting an auto-refresh command from the memory controller to the memory device, wherein responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for at least a portion of the first time interval; and concurrently, during at least a portion of the first time interval while the memory device is performing refresh operations, performing a calibration of the command interface of the memory device, wherein performing a calibration of the command interface of the memory device includes placing the command interface of the memory device into a loopback mode. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A memory controller to control a dynamic memory device that includes a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
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refresh logic to generate an auto-refresh command for transmission to the memory device, wherein responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh memory cells and the command interface is placed into a calibration mode for at least a portion of the first time interval; and calibration logic to concurrently, during at least a portion of the first time interval while the memory device is performing refresh operations, perform a calibration of the command interface of the memory device; wherein responsive to the auto-refresh command, the command interface is placed into a loopback mode for at least the portion of the first time interval. - View Dependent Claims (47, 48, 49)
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50. A dynamic memory device comprising:
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a plurality of memory banks, each bank including a plurality of rows of memory cells; a command interface operable to accept commands from a memory controller; refresh circuitry configured to refresh memory cells for a duration of a first time interval in response to an auto-refresh command from the memory controller; and control logic, in response to the auto-refresh command, to configure the command interface to, for at least a portion of the duration of the first time interval, not accept commands from the memory controller and to instead enter a calibration mode, wherein in the calibration mode, the command interface does not accept commands from the memory controller and is configured for calibration operations initiated by the memory controller; wherein the control logic, in response to the auto-refresh command, is to configure the command interface to enter a loopback mode, wherein in the loopback mode, the command interface receives a pattern on a first data path, and transmits the data pattern to the memory controller on a second data path. - View Dependent Claims (51)
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52. A method of operating a memory device in a system that includes the memory device and a memory controller, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:
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receiving an auto-refresh command from the memory controller at the memory device; responsive to the auto-refresh command, during a first time interval, refreshing memory cells in the memory device; and responsive to the auto-refresh command, placing the command interface from a normal operation mode into a calibration and loopback mode for at least a portion of the duration of the first time interval, wherein, in the calibration and loopback mode, the command interface receives a pattern on a first data path, and transmits the data pattern to the memory controller on a second data path, wherein the command interface accepts commands from the controller in the normal operation mode, and wherein the command interface does not accept commands from the controller in the calibration and loopback mode, and is instead configured for calibration operations initiated by the memory controller. - View Dependent Claims (53, 54, 55)
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56. A method of operating a memory controller, the method comprising:
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generating an auto-refresh command specifying a bank order for transmission to a dynamic memory device that includes a plurality of memory banks, each bank including a plurality of rows of memory cells, wherein responsive to the auto-refresh command, the memory device refreshes a row in each of the memory banks in accordance with the bank order, wherein the specified bank order specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the auto-refresh command. - View Dependent Claims (57)
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58. A dynamic memory device comprising:
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a plurality of memory banks, each bank including a plurality of rows of memory cells; a command interface to receive a refresh command, the auto-refresh command specifying a bank order for the plurality of memory banks; at least one row refresh register to store a value that identifies a respective row of the plurality of rows of memory cells in each bank; and control circuitry coupled to the command interface, the row refresh register and the plurality of memory banks, the control circuitry being configured to sequentially refresh the respective row in the plurality of memory banks, in the specified bank order, wherein the specified bank order specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the received refresh command. - View Dependent Claims (59, 60, 61, 62)
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63. A method of controlling a dynamic memory device organized in a plurality memory banks that each include a plurality of rows of memory cells, the method comprising:
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generating an auto-refresh command, the auto-refresh command specifying a bank order for the plurality of memory banks; and issuing the auto-refresh command to the memory device to place the memory device in an operating state in which control circuitry within the memory device sequentially refreshes memory cells in the memory banks in the specified bank order, wherein the specified bank order specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the refresh command. - View Dependent Claims (64)
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65. A method of controlling a memory device having a row refresh register, the memory device being organized in a plurality of memory banks, each memory bank including a plurality of rows of memory cells, the method comprising:
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issuing memory access commands to the memory device to access the rows of memory cells therein; issuing to the memory device, between any two of the memory access commands, a first single auto-refresh command to initiate refresh operations on respective rows of memory banks of the memory device, in a bank order specified by the first auto-refresh command, wherein the bank order specified by the first single auto-refresh command specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the first single auto-refresh command. - View Dependent Claims (66)
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Specification