METHOD AND APPARATUS FOR CACHE CONTROL

• US 20110283124A1
• Filed: 05/11/2010
• Published: 11/17/2011
• Est. Priority Date: 05/11/2010
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hack, Norman M., Kalamatianos, John, Owen, Jonathan M., Steinman, Maurice B., Branover, Alexander
• Granted Patent: US 8,412,971 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

Claims

1. A method comprising:

responsive lo a processor having changed from a first operating point to a second operating point, selectively altering power of one or more ways of a cache memory; and

processing one or more instructions in the processor subsequent to altering power of the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was altered.

2. The method as recited in claim 1, wherein altering power of one or more cache ways comprises removing power from the one or more cache ways.

3. The method as recited in claim 1, wherein changing the operating point comprises changing an operating voltage and a clock frequency at which the processor operates.

4. The method as recited in claim 1, wherein changing the operating point comprises changing from a high performance operating mode to a power saving mode.

5. The method as recited in claim 1, further comprising removing power from half of a plurality of currently active ways of the cache memory responsive lo changing the operating point.

6. The method as recited in claim 1, further comprising:

changing the operating point of the processor from the second operating point to a third operating point; and

selectively removing power from one or more additional ways of a cache memory responsive to changing the operating point.

7. The method as recited in claim 6, further comprising:

changing the operating point of a processor from the third operating point to one of the first or second operating points; and

selectively applying power to one or more ways from which power was removed when the operating point was changed from the first operating point to the second operating point or the second operating point to the third operating point.

8. The method as recited in claim 5, further comprising:

changing the operating point of the processor from the second operating point to a third operating point;

reading a CIPS (committed instructions per second) value;

calculating a sum of a threshold value and a guard band value;

comparing the CIPS value to the threshold value and the sum;

selectively removing power from one or more additional ways of a cache memory responsive to changing to the third operating point if the CIPS value is less than the threshold value; and

powering on all ways of the cache memory if the CIPS value is greater than the sum;

wherein no additional ways of the cache memory are powered on or off if the CIPS value is greater than the threshold value and less than the sum.

9. The method as recited in claim 1, further comprising sending a notification to one or more additional processors indicating that one or more ways of the cache memory have been powered down.

10. The method as recited in claim 1, further comprising:

determining an amount of time that has elapsed since selectively removing power from one or more ways of the cache memory;

comparing the amount of time to a first time threshold; and

preventing additional ways of the cache memory from being powered down if the amount of time is less than the first time threshold.

11. The method as recited in claim 10, further comprising:

comparing the amount of time to a second time threshold; and

preventing additional ways of the cache memory from being powered up if the second amount of time is less than the second time threshold.

12. A processor comprising:

a power management unit configured to selectively alter power of a first subset of the plurality of ways of a cache memory responsive to at least one execution unit changing an operating point from a first operating point to a second operating point; and

wherein the at least one execution unit of the processor is configured to. subsequent to selectively altering power of the first subset of the plurality of ways, access one or more ways of a second subset of the plurality of ways from which power was altered.

13. The processor as recited in claim 12, wherein altering power of the first subset of ways comprises removing power from the first subset of ways.

14. The processor as recited in claim 12, wherein the power management unit is further configured to change the operating point of the processor by causing a change to an operating voltage and a clock frequency at which the processor operates.

15. The processor as recited in claim 12, wherein the processor is configured lo operate in a high performance mode and in a power saving mode, wherein changing the operating point comprises changing from a high performance operating mode to a power saving mode.

16. The processor as recited in claim 12, wherein the power management unit is configured to power down one half of a plurality of active ways of the cache memory responsive to changing the operating point.

17. The processor as recited in claim 12, wherein the power management unit is further configured to selectively remove power from one or more additional ways of a cache memory responsive to the processor changing the operating point from the second operating point to a third operating point.

18. The processor as recited in claim 17, wherein the power management unit is configured to selectively apply power to one or more ways from which power was previously removed responsive to changing the operating point of the processor from the third operating point to one of the first or second operating points.

19. The processor as recited in claim 12, wherein the power management unit is further configured to send a notification to one or more additional processors to indicate that one or more ways of the cache memory have been powered down.

20. A method comprising:

calculating a sum of a first threshold value and a second threshold value;

comparing a workload indicator value to first the threshold value and the second threshold value;

selectively removing power from a subset of a plurality of ways of a cache memory if a workload indicator value of a processor is less than a first threshold value; and

powering on any previously powered down ways of the cache memory if the workload indicator value is greater than a second threshold;

wherein power to ways of the cache memory is altered if the workload indicator value is greater than the first threshold value and less than the second threshold.

21. The method as recited in claim 20, further comprising determining the workload indicator value for a processor that includes the cache memory.

22. The method as recited in claim 20, wherein the second threshold value is a sum of the first threshold value and a guard band value.

23. The method as recited in claim 20, wherein the workload indicator value is a CIPS (committed instructions per second) value.

24. The method as recited in claim 20, further comprising:

determining an amount of time that has elapsed since selectively removing power from one or more ways of the cache memory;

comparing the amount of time to a first time threshold; and

preventing additional ways of the cache memory from being powered down if the amount of time is less than the first time threshold.

25. The method as recited in claim 20, further comprising;

sending a first notification to one or more additional processors if the first subset of ways is powered down, the first notification indicating the powering down of the first subset of ways; and

sending a second notification to the one or more additional processor responsive to powering up any previously powered down ways of the cache memory, the second notification indicating that the previously powered down ways of the cache memory have been powered up.

31. The computer readable medium as recited in claim 25, wherein the data structure comprises one or more of the following types of data:

HDL (high-level design language) data;

RTL (register transfer level) data;

Graphic Data System (GDS) II data.

26. A method comprising:

changing a performance state of a processor from a first performance state to a second performance state, wherein the first performance state comprises operating a core of the processor at a first voltage and a first clock frequency, and wherein the second performance state comprises operating the core at a second voltage less than the first voltage and a second clock frequency less than the first clock frequency;

selectively removing power from one or more ways of a cache memory responsive to changing the performance state; and

processing one or more instructions in the core of the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes the core accessing one or more ways of the cache memory from which power was not removed.

27. The method as recited in claim 26, further comprising;

changing the performance state of the processor from the second performance state to a third performance state, wherein the third performance state comprises operating the core at a third voltage and a third clock frequency, the third voltage being less than the second voltage and the third clock frequency being less than the second clock frequency;

selectively removing power from one or more additional ways of the cache memory responsive to changing from the second performance state to the third performance state; and

processing one or more instructions in the core of the processor subsequent to removing power from the one or more additional ways, wherein said processing includes the core accessing one or more ways of the cache memory from which power was not removed.

28. The method as recited in claim 27, further comprising:

changing the performance state of the processor from the third performance state to one of the first or second performance states; and

selectively powering up one or more of the cache ways that were previously powered down.

29. The method as recited in claim 26, further comprising comparing an amount of time since power was selectively removed from the one or more of the cache ways to a first residency requirement and a second residency requirement, wherein the method further includes preventing any additional cache ways from being powered down if the amount of time is less than the first residency requirement and preventing any additional cache ways from being powered up if the amount of time is less than the second residency requirement.

30. A computer readable medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:

a power management unit configured to selectively alter power of a first subset of the plurality of ways of a cache memory responsive to at least one execution unit changing an operating point from a first operating point to a second operating point; and

wherein the at least one execution unit is configured to, subsequent to selectively altering power of the first subset of the plurality of ways, access one or more ways of a second subset of the plurality of ways from which power was altered.