SYSTEM-ON-CHIP AND DEBUGGING METHOD THEREOF

• US 20110283141A1
• Filed: 05/06/2011
• Published: 11/17/2011
• Est. Priority Date: 05/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, JAEGON, Ahn, Hyunsun
• Granted Patent: US 8,656,220 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.

Claims

1. A system-on-chip, comprising:

a core;

a plurality of power domain blocks; and

a power control circuit including a debug circuit,

wherein the power control circuit is configured to control a power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.

2. The system-on-chip of claim 1, further comprising:

at least one input/output pin configured to allow the debug circuit to communicate with an external entity.

3. The system-on-chip of claim 2, further comprising:

an input/output interface configured to communicate with an external entity through a plurality of input/output pins,

wherein the debug circuit and the input/output interface are configured to share at least one of the plurality of input/output pins.

4. The system-on-chip of claim 2, further comprising:

a debugging pin, different from the at least one input/output pin, configured to allow for debugging of the core.

5. The system-on-chip of claim 1, further comprising:

a logic value debugger disposed in the debug circuit, configured to output a voltage level of at least one node of the power control circuit to an external entity, in response to a debug control signal during a debugging operation of the power control circuit.

6. The system-on-chip of claim 5, wherein the power control circuit is configured to enter an operation maintenance mode during the debugging operation of the power control circuit.

7. The system-on-chip of claim 1, further comprising:

an inserting debugger disposed in the debug circuit, configured to vary a voltage level of at least one node in the power control circuit, in response to a debug control signal during a debugging operation of the power control circuit.

8. The system-on-chip of claim 7, further comprising:

a multiplexer disposed in the debug circuit and coupled between an output of a first function block of the power control circuit and an input of a second function block of the power control circuit,

wherein the multiplexer is configured to transmit one of the output of the first function block and a debugging input signal from the inserting debugger to the input of the second function block under a control of the inserting debugger.

9. The system-on-chip of claim 1, further comprising:

a variation debugger disposed in the debug circuit, configured to output a variation value based on a variation over time of a voltage of at least one node in the power control circuit to an external entity, in response to a debug control signal during a debugging operation of the power control circuit.

10. The system-on-chip of claim 1, further comprising:

an inserting debugger disposed in the debug circuit, configured to vary a voltage level of a first node in the power control circuit; and

a logic value debugger disposed in the debug circuit, configured to output a voltage level of a second node in the power control circuit, based on the variation of the voltage level of the first node, to an external entity during a debugging operation of the power control circuit.

11. The system-on-chip of claim 1, further comprising:

an inserting debugger disposed in the debug circuit, configured to vary a voltage level of a first node in the power control circuit; and

a variation debugger disposed in the debug circuit, configured to output a time-lapse voltage variation of a second node in the power control circuit, based on the variation of the voltage level of the first node, to an external entity during a debugging operation of the power control circuit.

12. The system-on-chip of in claim 1, further comprising:

a joint test action group (JTAG) interface, configured to allow the core to be debugged based on a JTAG protocol.

13. A debugging method for a system-on-chip, comprising:

debugging an operation of the system-on-chip through a debugging pin disposed on the system-on-chip; and

debugging a power control circuit of the system-on-chip through a plurality of input/output pins, different from the debugging pin, disposed on the system-on-chip.

14. The debugging method of claim 13, wherein debugging the power control circuit comprises detecting a voltage level of at least one first node in the power control circuit.

15. The debugging method of claim 14, wherein debugging the power control circuit further comprises varying the voltage level of at least one node, other than the at least one first node, in the power control circuit.

16. The debugging method of claim 14, wherein debugging the power control circuit further comprises monitoring a voltage variation of at least one node, other than the at least one first node, in the power control circuit.

17. The debugging method of claim 14, wherein debugging the power control circuit further comprises:

varying the voltage level of the at least one first node in the power control circuit; and

detecting a voltage level of at least one second node in the power control circuit, based on the variation of the voltage level of the at least one first node.

18. The debugging method of claim 14, wherein debugging the power control circuit further comprises:

varying the voltage level of the at least one first node in the power control circuit; and

monitoring a voltage variation of at least one second node in the power control circuit, based on the variation of the voltage level of the at least one first node.