EMBEDDED GUARD-SANITIZER
First Claim
1. An apparatus comprising:
- a processor;
a volatile, high-to-low working memory partition connected to the processor;
a volatile, low-to-high working memory partition connected to the processor;
a high-side, input/output section providing an interface to a high-side network or data bus, and configured to send messages to the high-to-low working memory, and to receive messages from the low-to-high working memory;
a low-side, input/output section providing an interface to a low-side network or data bus, and configured to send messages to the low-to-high working memory, and to receive messages from the high-to-low working memory;
a first non-volatile memory for storing a binary rule set image, whereby the processor controls the transfer of messages between the high-side input/output section and the low-side input/output section in accordance with the rule set; and
a second non-volatile, memory for storing firmware for controlling executive functions of the apparatus.
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Accused Products
Abstract
An apparatus includes a processor; a volatile, high-to-low working memory partition connected to the processor; a volatile, low-to-high working memory partition connected to the processor; a high-side, input/output section providing an interface to a high-side network or data bus, and configured to send messages to the high-to-low working memory, and to receive messages from the low-to-high working memory; a low-side, input/output section providing an interface to a low-side network or data bus, and configured to send messages to the low-to-high working memory, and to receive messages from the high-to-low working memory; a first non-volatile memory for storing a rule set binary image, whereby the processor controls the transfer of messages between the high-side input/output section and the low-side input/output section in accordance with the rule set; and a second non-volatile, memory for storing firmware for controlling executive functions of the apparatus.
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Citations
16 Claims
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1. An apparatus comprising:
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a processor; a volatile, high-to-low working memory partition connected to the processor; a volatile, low-to-high working memory partition connected to the processor; a high-side, input/output section providing an interface to a high-side network or data bus, and configured to send messages to the high-to-low working memory, and to receive messages from the low-to-high working memory; a low-side, input/output section providing an interface to a low-side network or data bus, and configured to send messages to the low-to-high working memory, and to receive messages from the high-to-low working memory; a first non-volatile memory for storing a binary rule set image, whereby the processor controls the transfer of messages between the high-side input/output section and the low-side input/output section in accordance with the rule set; and a second non-volatile, memory for storing firmware for controlling executive functions of the apparatus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification