LAYOUT METHOD, LAYOUT SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING LAYOUT PROGRAM OF SEMICODUCTOR INTEGRATED CIRCUIT

• US 20110283248A1
• Filed: 05/03/2011
• Published: 11/17/2011
• Est. Priority Date: 05/13/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Irie, Kazuyuki
• Granted Patent: US 8,751,991 B2
• Time in Patent Office: Days
• US Class Current: 716/120
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A layout method of a semiconductor integrated circuit according to the present invention includes selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route.

Claims

1. A layout method of a semiconductor integrated circuit, comprising:

selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and

replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route.

2. The layout method according to claim 1, comprising:

executing timing verification when it is assumed that replacement is performed with the multi-data input/output sequential circuit for a former-stage path and a latter-stage path of each of the M pieces of sequential circuits that are selected using arrangement information of the M pieces of sequential circuits that are selected and arrangement information of the multi-data input/output sequential circuit when it is assumed that the replacement is performed; and

performing replacement with the multi-data input/output sequential circuit when there is no timing error in all the former-stage paths and the latter-stage paths in which the timing verification is executed.

3. The layout method according to claim 2, comprising executing the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using a clock skew value after the CTS is executed.

4. The layout method according to claim 1, comprising:

executing timing analysis for the N pieces of sequential circuits;

selecting a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits; and

replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

5. The layout method according to claim 3, comprising:

calculating a clock skew value after executing CTS;

selecting a part or all of the sequential circuits corresponding to a path in which the clock skew value exceeds a predetermined value as the M pieces of sequential circuits; and

replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

6. The layout method according to claim 1, comprising:

selecting the M pieces of sequential circuits from the N pieces of sequential circuits before CTS is executed;

replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit;

executing CTS based on arrangement information after the replacement;

selecting a plurality of sequential circuits from a sequential circuit which is not replaced among the N pieces of sequential circuits and the multi-data input/output sequential circuit after replacement after the CTS is executed; and

replacing the plurality of sequential circuits that are selected with the one multi-data input/output sequential circuit in consideration of a clock skew value after the CTS is executed.

7. The layout method according to claim 2, comprising executing the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using an OCV value of a clock.

8. The layout method according to claim 2, comprising:

executing timing analysis for the N pieces of sequential circuits;

selecting a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits; and

replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

9. The layout method according to claim 3, comprising:

executing timing analysis for the N pieces of sequential circuits;

selecting a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits; and

replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

10. The layout method according to claim 2, comprising:

selecting the M pieces of sequential circuits from the N pieces of sequential circuits before CTS is executed;

replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit;

executing CTS based on arrangement information after the replacement;

selecting a plurality of sequential circuits from a sequential circuit which is not replaced among the N pieces of sequential circuits and the multi-data input/output sequential circuit which is replaced after the CTS is executed; and

replacing the plurality of sequential circuits that are selected with the one multi-data input/output sequential circuit in consideration of a clock skew value after the CTS is executed.

11. A layout system of a semiconductor integrated circuit using a computer, the computer comprising:

a storage unit that stores arrangement information of N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and

a control unit that executes layout of the sequential circuits in the semiconductor integrated circuit, wherein the control unit comprises;

a selection unit that selects M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from the N pieces of sequential circuits; and

a replacement unit that replaces the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives a clock distributed from the clock route.

12. The layout system according to claim 11, wherein

the control unit further comprises a timing verification unit that executes timing verification when it is assumed that replacement is performed with the multi-data input/output sequential circuit for a former-stage path and a latter-stage path of each of the M pieces of sequential circuits that are selected using arrangement information of the M pieces of sequential circuits that are selected and arrangement information of the multi-data input/output sequential circuit when it is assumed that the replacement is performed, and

the replacement unit performs replacement with the multi-data input/output sequential circuit when there is no timing error in all the former-stage paths and the latter-stage paths in which the timing verification is executed.

13. The layout system according to claim 12, wherein the timing verification unit executes the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using a clock skew value after the CTS is executed.

14. The layout system according to claim 11, wherein

the control unit further comprises a timing analysis unit that executes timing analysis for the N pieces of sequential circuits,

the selection unit selects a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits, and

the replacement unit replaces the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

15. The layout system according to claim 13, wherein

the control unit further comprises a calculation unit that calculates a clock skew value after the CTS is executed,

the selection unit selects a part or all of the sequential circuits corresponding to a path in which the clock skew value exceeds a predetermined value as the M pieces of sequential circuits, and

the replacement unit replaces the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

16. A non-transitory computer readable medium storing a layout program of a semiconductor integrated circuit that makes a computer to execute processing including:

selection processing that selects M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and

replacement processing that replaces the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route.

17. The non-transitory computer readable medium storing the layout program according to claim 16, further comprising:

timing verification processing that executes timing verification when it is assumed that replacement is performed with the multi-data input/output sequential circuit for a former-stage path and a latter-stage path of each of the M pieces of sequential circuits that are selected using arrangement information of the M pieces of sequential circuits that are selected and arrangement information of the multi-data input/output sequential circuit when it is assumed that the replacement is performed;

wherein the replacement processing performs replacement with the multi-data input/output sequential circuit when there is no timing error in all the former-stage paths and the latter-stage paths in which the timing verification is executed.

18. The non-transitory computer readable medium storing the layout program according to claim 17, wherein the timing verification processing executes the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using a clock skew value after the CTS is executed.

19. The non-transitory computer readable medium storing the layout program according to claim 16, further comprising timing analysis processing that executes timing analysis for the N pieces of sequential circuits;

wherein

the selection processing selects a part or all of the sequential circuits in which timing error is occurred by the timing analysis processing as the M pieces of sequential circuits, and

the replacement processing replaces the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.

20. The non-transitory computer readable medium storing the layout program according to claim 18, further comprising a calculation processing that calculates a clock skew value after the CTS is executed, wherein

the selection processing selects a part or all of the sequential circuits corresponding to a path in which the clock skew value exceeds a predetermined value as the M pieces of sequential circuits, and

the replacement processing replaces the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit.