THROUGH SILICON VIA FILLING USING AN ELECTROLYTE WITH A DUAL STATE INHIBITOR

• US 20110284386A1
• Filed: 05/18/2011
• Published: 11/24/2011
• Est. Priority Date: 05/19/2010
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Willey, Mark J., Mayer, Steven T.
• Granted Patent: US 8,992,757 B2
• Time in Patent Office: Days
• US Class Current: 205/96
• CPC Class Codes: C25D 21/12 Process control or regulation controlling or regulating in general G05
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for electrofilling large, high aspect ratio recessed features with copper without depositing substantial amounts of copper in the field region is provided. The method allows completely filling recessed features having aspect ratios of at least about 5:1 such as at least about 10:1, and widths of at least about 1 μm in a substantially void-free manner without depositing more than 5% of copper in the field region (relative to the thickness deposited in the recessed feature). The method involves contacting the substrate having one or more large, high aspect ratio recessed features (such as a TSVs) with an electrolyte comprising copper ions and an organic dual state inhibitor (DSI) configured for inhibiting copper deposition in the field region, and electrodepositing copper under potential-controlled conditions, where the potential is controlled not exceed the critical potential of the DSI.

Claims

1. A method of electrochemically filling large high aspect ratio recessed features with metal without depositing a thick layer of metal on the field region of a substrate, the method comprising:

(a) providing a substrate having a large high aspect ratio recessed feature to an electroplating apparatus, wherein the recessed feature has a diameter or width of at least about 1 μ

m and an aspect ratio of at least about 5;

1, and;

(b) electroplating metal in the recessed feature by contacting the substrate with an electroplating solution comprising (i) metal ions; and

(ii) an organic dual-state inhibitor (DSI) configured for inhibiting metal deposition in the field region, while electrically biasing the substrate under potential-controlled conditions, wherein after filling the feature, the ratio of the metal layer thickness deposited on the field to the metal layer thickness deposited in the feature is not greater than about 0.05.

2. The method of claim 1, wherein the metal is copper.

3. The method of claim 1, wherein the recessed feature is a through silicon via (TSV).

4. The method of claim 1, wherein the recessed feature has an aspect ratio of at least about 15:

1.

5. The method of claim 1, wherein electrically biasing the substrate under potential-controlled conditions comprises controlling the potential, such that it does not exceed the critical potential of the dual state inhibitor for selected plating conditions.

6. The method of claim 1, wherein the potential is controlled using a reference electrode positioned in the proximity of the substrate.

7. The method of claim 1, wherein the potential is controlled using a reference electrode positioned in the proximity of the substrate, wherein the reference electrode is an unpolarized metal electrode comprising the same metal that is being electroplated.

8. The method of claim 1, wherein the potential is controlled using a reference electrode positioned in the proximity of the substrate, wherein the reference electrode is immersed into a solution that is substantially free of the DSI additive.

9. The method of claim 1, wherein the dual-state inhibitor suppresses the current in the field region to less than about 2 mA/cm².

10. The method of claim 1, wherein the critical potential of the dual-state inhibitor is at least about −

0.15 V versus the open circuit potential.

11. The method of claim 1, wherein at about the critical potential the current increases at least 0.1 mA/cm² per 1 mV.

12. The method of claim 1, wherein the electroplating solution comprises copper ions at a concentration of at least about 40 g/L.

13. The method of claim 1, wherein the electroplating solution further comprises sulfuric and/or methanesulfonic acid at a concentration of at least about 40 g/L.

14. The method of claim 1, wherein the electroplating solution further comprises an electroplating accelerator, selected from the group consisting of MSA, SPS, and DPS.

15. The method of claim 1, wherein the electroplating solution further comprises an electroplating suppressor, selected from the group consisting of PEG and PEO.

16. The method of claim 1, wherein the DSI compound is a quartenary ammonium salt, which has at least one alkyl or aralkyl substituent with at least 7 carbon atoms.

17. The method of claim 1, wherein the DSI compound is selected from the group consisting of a benzalkonium salt, a thonzonium salt, a dodecyltrimethylammonium salt, and BDHAC.

18. The method of claim 1, wherein the plating is performed at a temperature range of between about 20 and 60 degrees C.

19. The method of claim 1, further comprising determining plating endpoint by the current response from the substrate.

20. The method of claim 1, wherein the substrate is electrically biased within about 1 second after it is contacted with the plating solution.

21. The method of claim 1, wherein the substrate is rotated at between about 5-120 rpm during plating.

22. The method of claim 1, further comprising rotating the substrate during electroplating, and reducing the rotation rate of the substrate during plating.

23. The method of claim 1, wherein the electrical biasing and the controlling of the potential during plating, comprises:

(i) determining a current waveform imposed on the plating cell that creates an equivalent to potential-controlled conditions, and (iii) applying said current waveform to the substrate during electroplating.

24. The method of claim 1, wherein the electroplating solution is substantially free of chloride.

25. The method of claim 1, wherein the electroplating solution comprises more than one DSI compound.

26. The method of claim 1, further comprising pre-wetting the substrate prior to plating, wherein the pre-wetting comprises:

(i) providing the substrate to a pre-wetting process chamber;

(ii) reducing pressure in the pre-wetting process chamber to a subatmospheric pressure; and

(iii) contacting the substrate with a pre-wetting fluid at a subatmospheric pressure to form a wetting layer on the substrate, wherein the pre-wetting fluid is substantially free of the DSI component.

30. A method of claim 1, further comprising the steps of:

applying photoresist to the substrate;

exposing the photoresist to light;

patterning the resist and transferring the pattern to the substrate;

and selectively removing the photoresist from the substrate.

31. The method of claim 30, wherein said patterning is performed to define large recessed features on the substrate prior to electroplating.

33. A non-transitory computer machine-readable medium comprising program instructions for control of an electroplating apparatus, the program instructions comprising:

code for performing a method of claim 1.

27. A method of electrochemically filling a through-silicon via (TSV) with copper metal, without depositing a thick layer of copper metal in a field region of a substrate, the method comprising:

(a) providing a substrate having a TSV recessed feature to a pre-wetting process chamber, wherein the TSV recessed feature has a diameter of at least about 1 micrometers and an aspect ratio of at least about 5;

1;

(b) reducing pressure in the pre-wetting process chamber to a subatmospheric pressure;

(c) contacting the substrate with a degassed pre-wetting fluid at a subatmospheric pressure to form a wetting layer on the substrate;

(d) transferring the pre-wetted substrate to an electroplating apparatus;

(e) contacting the substrate with an electroplating solution comprising (i) copper ions; and

(ii) an organic dual-state inhibitor configured for inhibiting copper deposition in the field region and

(f) electroplating copper with said electroplating solution to completely fill the TSV recessed feature, wherein, after the recessed feature is filled, the ratio of the copper layer thickness deposited on the field to the copper layer thickness deposited in the TSV is not greater than about 0.05.

28. An aqueous electroplating bath solution for filling large high aspect ratio recessed features with copper, without depositing a thick layer of copper in the field region, the aqueous solution comprising:

(a) copper ions; and

(b) an organic dual state inhibitor configured for inhibiting deposition of copper in the field region, wherein the organic dual state inhibitor is a quartenary ammonium salt, having one or more alkyl or aralkyl N-substituents with at least seven carbon atoms.

29. An electroplating apparatus, comprising a controller with program instructions for electroplating metal in a recessed feature on a semiconductor substrate by contacting the substrate with an electroplating solution comprising (i) metal ions;

and (ii) an organic dual-state inhibitor (DSI) configured for inhibiting metal deposition in the field region, while electrically biasing the substrate under potential-controlled conditions, wherein after filling the feature, the ratio of the metal layer thickness deposited on the field to the metal layer thickness deposited in the feature is not greater than about 0.05.

32. A system comprising the electroplating apparatus of claim 29 and a stepper.