MEMORY DEVICE AND SEMICONDUCTOR DEVICE

• US 20110284838A1
• Filed: 05/13/2011
• Published: 11/24/2011
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SAITO, Toshihiko
• Granted Patent: US 9,299,723 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/18 Circuits for erasing optically
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

One object is to propose a memory device in which a period in which data is held can be ensured and memory capacity per unit area can be increased. The memory device includes a memory element, a transistor including an oxide semiconductor in an active layer for control of accumulating, holding, and discharging charge in the memory element, and a capacitor connected to the memory element. At least one of a pair of electrodes of the capacitor has a light-blocking property. Further, the memory device includes a light-blocking conductive film or a light-blocking insulating film. The active layer is positioned between the electrode having a light-blocking property and the light-blocking conductive film or the light-blocking insulating film.

Claims

1. A memory device comprising:

a memory cell comprising;

a transistor including an oxide semiconductor layer;

a capacitor in electrical contact with the transistor; and

a light-blocking layer,

wherein at least one of electrodes of the capacitor has a light-blocking property,

wherein the oxide semiconductor layer is sandwiched between the one of electrodes and the light-blocking layer, and

wherein at least one of the light-blocking layer and the one of electrodes covers a channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

2. The memory device according to claim 1, wherein both of the light-blocking layer and the one of electrodes covers the channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

3. The memory device according to claim 1, wherein at least one of the light-blocking layer and the one of electrodes completely covers the channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

4. The memory device according to claim 1,

wherein the light-blocking layer is a light-blocking insulating film,

wherein the light-blocking insulating film comprises a resin, and

wherein a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film is positioned between the oxide semiconductor layer and the light-blocking insulating film.

5. The memory device according to claim 1,

wherein the light-blocking layer is a wiring, and

wherein the wiring is connected to a source electrode or a drain electrode of the transistor.

6. The memory device according to claim 1, wherein when a wavelength at an absorption edge of an oxide semiconductor of the oxide semiconductor layer is λ

₀, in the light-blocking layer, transmittance of light having a wavelength longer than or equal to 100 nm and shorter than or equal to λ

₀+100 nm is lower than or equal to 50%.

7. The memory device according to claim 1, wherein when a wavelength at an absorption edge of an oxide semiconductor of the oxide semiconductor layer is λ

₀, in the one of electrodes having a light-blocking property, transmittance of light having a wavelength longer than or equal to 100 nm and shorter than or equal to λ

₀+100 nm is lower than or equal to 50%.

8. The memory device according to claim 1, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

9. The memory device according to claim 1, wherein hydrogen concentration of the oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.

10. A memory device comprising:

a memory cell comprising;

a first transistor including an oxide semiconductor layer;

a second transistor;

a capacitor; and

a light-blocking layer,

wherein the first transistor is configured to control supply of a potential to a gate electrode of the second transistor,

wherein the capacitor is configured to hold the potential of the gate electrode of the second transistor,

wherein at least one of electrodes of the capacitor has a light-blocking property,

wherein the oxide semiconductor layer is sandwiched between the one of electrodes and the light-blocking layer, and

wherein at least one of the light-blocking layer and the one of electrodes covers a channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

11. The memory device according to claim 10, wherein both of the light-blocking layer and the one of electrodes covers the channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

12. The memory device according to claim 10, wherein at least one of the light-blocking layer and the one of electrodes completely covers the channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

13. The memory device according to claim 10,

wherein the light-blocking layer is a light-blocking insulating film,

wherein the light-blocking insulating film comprises a resin, and

wherein a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film is positioned between the oxide semiconductor layer and the light-blocking insulating film.

14. The memory device according to claim 10,

wherein the light-blocking layer is a wiring, and

wherein the wiring is connected to a source electrode or a drain electrode of the first transistor.

15. The memory device according to claim 10, wherein when a wavelength at an absorption edge of an oxide semiconductor of the oxide semiconductor layer is λ

₀, in the light-blocking layer, transmittance of light having a wavelength longer than or equal to 100 nm and shorter than or equal to λ

₀+100 nm is lower than or equal to 50%.

16. The memory device according to claim 10, wherein when a wavelength at an absorption edge of an oxide semiconductor of the oxide semiconductor layer is λ

₀, in the one of electrodes having a light-blocking property, transmittance of light having a wavelength longer than or equal to 100 nm and shorter than or equal to λ

₀+100 nm is lower than or equal to 50%.

17. The memory device according to claim 10, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

18. The memory device according to claim 10, wherein hydrogen concentration of the oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.

19. A memory device comprising:

a memory cell comprising;

a transistor including an oxide semiconductor layer;

a capacitor; and

a light-blocking layer,

wherein the transistor is configured to hold charge of the capacitor,

wherein at least one of electrodes of the capacitor has a light-blocking property,

wherein the oxide semiconductor layer is sandwiched between the one of electrodes and the light-blocking layer, and

wherein at least one of the light-blocking layer and the one of electrodes covers a channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

20. The memory device according to claim 19, wherein both of the light-blocking layer and the one of electrodes covers the channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

21. The memory device according to claim 19, wherein at least one of the light-blocking layer and the one of electrodes completely covers the channel formation region of the oxide semiconductor layer in order to prevent light from entering the channel formation region.

22. The memory device according to claim 19,

wherein the light-blocking layer is a light-blocking insulating film,

wherein the light-blocking insulating film comprises a resin, and

wherein a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film is positioned between the oxide semiconductor layer and the light-blocking insulating film.

23. The memory device according to claim 19,

wherein the light-blocking layer is a wiring, and

wherein the wiring is connected to a source electrode or a drain electrode of the transistor.

24. The memory device according to claim 19, wherein when a wavelength at an absorption edge of an oxide semiconductor of the oxide semiconductor layer is λ

₀, in the light-blocking layer, transmittance of light having a wavelength longer than or equal to 100 nm and shorter than or equal to λ

₀+100 nm is lower than or equal to 50%.

25. The memory device according to claim 19, wherein when a wavelength at an absorption edge of an oxide semiconductor of the oxide semiconductor layer is λ

₀, in the one of electrodes having a light-blocking property, transmittance of light having a wavelength longer than or equal to 100 nm and shorter than or equal to λ

₀+100 nm is lower than or equal to 50%.

26. The memory device according to claim 19, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

27. The memory device according to claim 19, wherein hydrogen concentration of the oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.