SEMICONDUCTOR DEVICE

• US 20110284844A1
• Filed: 05/18/2011
• Published: 11/24/2011
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SASAKI, Toshinari, NODA, Kosei, ENDO, Yuta, SATO, Mizuho
• Granted Patent: US 9,263,589 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object of the present invention is to manufacture a semiconductor device where fluctuation in electrical characteristics is small and reliability is high in a transistor in which an oxide semiconductor is used. An insulating layer from which oxygen is released by heating is used as a base insulating layer of an oxide semiconductor layer which forms a channel. Oxygen is released from the base insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the base insulating layer and the oxide semiconductor layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.

Claims

1. A semiconductor device comprising:

an insulating layer configured to release oxygen by heating;

an oxide semiconductor layer over and in contact with the insulating layer;

a source electrode and a drain electrode over the oxide semiconductor layer, and electrically connected to the oxide semiconductor layer;

a gate insulating layer over the source electrode and the drain electrode; and

a gate electrode over the gate insulating layer,

wherein a part of the gate insulating layer is in contact with the oxide semiconductor layer; and

3. The semiconductor device according to claim 1, wherein the insulating layer comprises any of silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide.

5. The semiconductor device according to claim 1, wherein a released amount of oxygen molecules of the insulating layer is greater than or equal to 1×

10¹⁸/cm³ in thermal desorption spectroscopy.

6. The semiconductor device according to claim 1, wherein a released amount of oxygen molecules of the insulating layer is greater than or equal to 1×

10¹⁸/cm³ in thermal desorption spectroscopy.

7. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises a channel region, and a source region and a drain region,

wherein a resistance of the oxide semiconductor layer is reduced, and

wherein the source region and the drain region are connected to the source electrode and the drain electrode, respectively.

2. A semiconductor device comprising:

an insulating layer configured to release oxygen by heating;

a source electrode and a drain electrode provided over the insulating layer;

an oxide semiconductor layer electrically connected to the source electrode and the drain electrode;

a gate insulating layer provided over the oxide semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein a part of the oxide semiconductor layer is in contact with the insulating layer.

4. The semiconductor device according to claim 2, wherein the insulating layer comprises any of silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide.

8. The semiconductor device according to claim 2,

wherein the oxide semiconductor layer comprises a channel region, and a source region and a drain region,

wherein a resistance of the oxide semiconductor layer is reduced, and

wherein the source region and the drain region are connected to the source electrode and the drain electrode, respectively.

9. A method of manufacturing a semiconductor device comprising the steps of:

forming an insulating layer configured to release oxygen by heating, over a substrate;

forming an oxide semiconductor layer over and in contact with the insulating layer;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;

forming a gate insulating layer over the source electrode and the drain electrode, and

forming a gate electrode over the gate insulating layer,

wherein a part of the gate insulating layer is in contact with the oxide semiconductor layer.

11. The method of manufacturing a semiconductor device according to claim 9, wherein a channel region is formed in a portion of the oxide semiconductor layer overlapped with the gate electrode at the same time of a formation of a source region and a drain region by performing treatment for reducing resistance of the oxide semiconductor layer using the gate electrode as a mask.

13. The method of manufacturing a semiconductor device according to claim 9,

wherein the insulating layer is formed by a sputtering method or a plasma CVD method.

15. The method of manufacturing a semiconductor device according to claim 9, wherein the insulating layer is formed using an oxygen gas or a mixed gas of oxygen and argon by a sputtering method.

17. The method of manufacturing a semiconductor device according to claim 9, wherein the oxide semiconductor layer is formed by a sputtering method.

19. The method of manufacturing a semiconductor device according to claim 9, wherein a substrate temperature is higher than or equal to 100°

C. and lower than or equal to 450°

C. when the oxide semiconductor layer is formed.

21. The method of manufacturing a semiconductor device according to claim 9, wherein heat treatment is performed at a temperature of higher than or equal to 100°

C. and lower than or equal to 450°

C. after the oxide semiconductor layer is formed.

10. A method of manufacturing a semiconductor device comprising the steps of:

forming an insulating layer configured to release oxygen by heating, over a substrate;

forming a source electrode and a drain electrode over the insulating layer;

forming an oxide semiconductor layer electrically connected to the source electrode and the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer,

wherein a part of the oxide semiconductor layer is in contact with the insulating layer.

12. The method of manufacturing a semiconductor device according to claim 10, wherein a channel region is formed in a portion of the oxide semiconductor layer overlapped with the gate electrode at the same time of a formation of a source region and a drain region by performing treatment for reducing resistance of the oxide semiconductor layer using the gate electrode as a mask.

14. The method of manufacturing a semiconductor device according to claim 10, wherein the insulating layer is formed by a sputtering method or a plasma CVD method.

16. The method of manufacturing a semiconductor device according to claim 10, wherein the insulating layer is formed using an oxygen gas or a mixed gas of oxygen and argon by a sputtering method.

18. The method of manufacturing a semiconductor device according to claim 10, wherein the oxide semiconductor layer is formed by a sputtering method.

20. The method of manufacturing a semiconductor device according to claim 10, wherein a substrate temperature is higher than or equal to 100°

C. and lower than or equal to 450°

C. when the oxide semiconductor layer is formed.

22. The method of manufacturing a semiconductor device according to claim 10, wherein heat treatment is performed at a temperature of higher than or equal to 100°

C. and lower than or equal to 450°

C. after the oxide semiconductor layer is formed.