3D INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

• US 20110284992A1
• Filed: 09/19/2010
• Published: 11/24/2011
• Est. Priority Date: 05/24/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Zhu, Huilong
• Granted Patent: US 8,541,305 B2
• Time in Patent Office: Days
• US Class Current: 257/611
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit.

Claims

1. A three-dimensional integrated circuit structure, comprising:

a semiconductor substrate;

at least one semiconductor device formed on the upper surface of the semiconductor substrate;

a through-Si-via extending through the semiconductor substrate, and comprising a conductive via and an insulating layer covering sidewalls of the conductive via;

an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and

a diffusion trapping region formed on the lower surface of the semiconductor substrate and surrounding the through-Si-via.

2. The structure of claim 1, wherein the diffusion trapping region comprises any one or more ions of Ar, Xe, Ge, and P.

3. The structure of claim 1, wherein the implantation depth in the diffusion trapping region is in the range of about 10-1000 nm.

4. The structure of claim 1, wherein the implantation dose of ions in the diffusion trapping region is in the range of about 10¹³-10¹⁶/cm².

5. The structure of claim 1, wherein the diffusion trapping region is a trapping region for metal ions.

6. The structure of claim 1, wherein the diffusion trapping region is formed at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

18. The structure of claim 2, wherein the diffusion trapping region is former at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

19. The structure of claim 3, wherein the diffusion trapping region is former at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

20. The structure of claim 4, wherein the diffusion trapping region is former at the lower surface of the semiconductor substrate by self-aligning the outer periphery of the through-Si-via.

7. A manufacturing method of a 3D integrated circuit, comprising:

providing a semiconductor substrate with at least one semiconductor device formed on the upper surface of the semiconductor substrate;

forming a through-Si-via in the semiconductor substrate, wherein the through-Si-via comprises a conductive via and an insulating layer covering sidewalls of the conductive via;

forming an interconnection structure connecting the at least one semiconductor device and the through-Si-via;

selectively etching the lower surface of the semiconductor substrate to stop at the insulating layer of the through-Si-via;

forming a diffusion trapping region on the lower surface; and

removing a part of the through-Si-via higher than the lower surface.

8. The method of claim 7, further comprising depositing a protection layer on the lower surface after forming the diffusion trapping region, and selectively removing the protection layer at the same time when removing the part of the through-Si-via higher than the lower surface.

9. The method of claim 7, wherein forming the diffusion trapping region on the lower surface comprises forming the diffusion trapping region by self-aligning the outer periphery of the through-Si-via.

10. The method of claim 7, wherein forming the diffusion trapping region comprises implanting ions into the lower surface, and the implanted ions comprise any one or more of Ar, Xe, Ge, and P.

11. The method of claim 10, wherein the depth for the ions implantation is controlled to be in the range of about 10-1000 nm.

12. The method of claim 10, wherein the implantation dose of the ions is in the range of about 10¹³-10¹⁶/cm².

13. The method of claim 7, further comprises the lower surface of the semiconductor substrate being grinded to be thinned before selectively etching the lower surface.

14. The method of claim 7, wherein the diffusion trapping region is a trapping region for metal ions.

15. The method of claim 8, wherein the diffusion trapping region is a trapping region for metal ions.

16. The method of claim 9, wherein the diffusion trapping region is a trapping region for metal ions.

17. The method of claim 10, wherein the diffusion trapping region is a trapping region for metal ions.