PACKAGE SYSTEMS HAVING INTERPOSERS

• US 20110285005A1
• Filed: 05/18/2010
• Published: 11/24/2011
• Est. Priority Date: 05/18/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIN, Jing-Cheng, YU, Chen-Hua, LIN, Yung-Chi
• Granted Patent: US 8,866,301 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

Claims

1. A package system comprising:

an interposer comprising;

at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer; and

a first interconnect structure disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures; and

a first integrated circuit disposed over the interposer, the first integrated circuit being electrically coupled with the first interconnect structure.

2. The package system of claim 1, wherein the plurality of electrical connection structures are disposed straight through the at least one molding compound layer.

3. The package system of claim 1, wherein the interposer further comprises:

a second interconnect structure disposed under a second surface of the at least one molding compound layer that is opposite to the first surface.

4. The package system of claim 3, wherein a metallic line pitch of the second interconnect structure is larger than a metallic line pitch of the first interconnect structure.

5. The package system of claim 1, further comprising:

a second integrated circuit electrically coupled with the first interconnect structure, wherein the at least one molding compound layer is disposed at least partially around at least one side edge of the second integrated circuit.

6. The package system of claim 5, wherein the second integrated circuit is disposed within the at least one molding compound layer.

7. The package system of claim 1, wherein the interposer further comprises:

a plurality of barrier structures each of which is disposed at least partially around at least one side edge of one of the plurality electrical connection structures.

8. The package system of claim 1, further comprising:

a cap layer covering the first integrated circuit, wherein a coefficient of thermal expansion (CTE) of the cap layer is substantially equal to a CTE of the at least one molding compound layer.

9. A package system comprising:

an interposer comprising;

at least one molding compound layer including a plurality of electrical connection structures straight through the at least one molding compound layer;

a first interconnect structure disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures; and

a second interconnect structure disposed under a second surface of the at least one molding compound layer that is opposite to the first surface; and

a first integrated circuit disposed over the interposer, the first integrated circuit being electrically coupled with the first interconnect structure.

10. The package system of claim 9, wherein a metallic line pitch of the second interconnect structure is larger than a metallic line pitch of the first interconnect structure.

11. The package system of claim 9, further comprising:

a second integrated circuit electrically coupled with the first interconnect structure, wherein the at least one molding compound layer is disposed at least partially around at least one side edge of the second integrated circuit.

12. The package system of claim 11, wherein the second integrated circuit is disposed within the at least one molding compound layer.

13. The package system of claim 9, wherein the interposer further comprises:

a plurality of barrier structures each of which is disposed at least partially around at least one side edge of one of the plurality electrical connection structures.

14. The package system of claim 9, further comprising:

a cap layer covering the first integrated circuit, wherein a coefficient of thermal expansion (CTE) of the cap layer is substantially equal to a CTE of the at least one molding compound layer.

15. A package system comprising:

an interposer comprising;

at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer, wherein the at least one molding layer has a first coefficient of thermal expansion (CTE); and

a first interconnect structure disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures;

a first integrated circuit disposed over the interposer, the first integrated circuit being electrically coupled with the first interconnect structure;

an underfill material disposed between the interposer and the first integrated circuit, wherein the underfill material has a second CTE and the second CTE is substantially equal to the first CTE; and

a cap layer disposed over the interposer, the cap layer covering the first integrated circuit, wherein the cap layer has a third CTE and the third CTE is substantially equal to the first CTE.

16. The package system of claim 15, wherein the plurality of electrical connection structures are disposed straight through the at least one molding compound layer.

17. The package system of claim 15, wherein the interposer further comprises:

a second interconnect structure disposed under a second surface of the at least one molding compound layer that is opposite to the first surface, wherein a metallic line pitch of the second interconnect structure is larger than a metallic line pitch of the first interconnect structure.

18. The package system of claim 15, further comprising:

a second integrated circuit electrically coupled with the first interconnect structure, wherein the at least one molding compound layer is disposed at least partially around at least one side edge of the second integrated circuit.

19. The package system of claim 18, wherein the second integrated circuit is disposed within the at least one molding compound layer.

20. The package system of claim 15, wherein the interposer further comprises:

a plurality of barrier structures each of which is disposed at least partially around at least one side edge of one of the plurality electrical connection structures.