NONVOLATILE MEMORY DEVICE HAVING A TRANSISTOR CONNECTED IN PARALLEL WITH A RESISTANCE SWITCHING DEVICE

• US 20110286258A1
• Filed: 05/24/2010
• Published: 11/24/2011
• Est. Priority Date: 05/24/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lee, Feng-Ming, Chen, Yi-Chou, Chien, Wei-Chih
• Granted Patent: US 8,331,127 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0009 RRAM elements whose operation depends upon chemical change
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Claims

1. A memory device comprising an array of memory cells, at least one of the memory cells comprising:

a transistor having a first terminal, a second terminal, and a gate terminal, the transistor being configured to be switchable between a plurality of different threshold voltages associated with respective memory states; and

a resistance switching device connected in parallel with the transistor such that the resistance switching device is connected to the first and second terminals of the transistor, the resistance switching device being configured to be switchable between a plurality of different resistances associated with respective memory states.

2. The memory device of claim 1, wherein the resistance switching device includes first and second interface regions having respective different resistance switching characteristics.

3. The memory device of claim 2, wherein at least one of the first and second interface regions includes at least a portion of a tungsten oxide layer.

4. The memory device of claim 2, wherein the resistance switching characteristics of the first interface region are symmetrical to the resistance switching characteristics of the second interface region.

5. The memory device of claim 2, wherein the resistance switching characteristics of the first interface region are asymmetrical to the resistance switching characteristics of the second interface region.

6. The memory device of claim 1, wherein the resistance switching device includes a first programmable metallization cell.

7. The memory device of claim 6, wherein the resistance switching device includes a second programmable metallization cell.

8. The memory device of claim 7, wherein the first programmable metallization cell includes a first solid electrolyte layer and the second programmable metallization cell includes a second solid electrolyte layer.

9. The memory device of claim 8, wherein the resistance switching device includes an oxidizable electrode layer disposed between the first and second solid electrolyte layers.

10. The memory device of claim 7, wherein the first programmable metallization cell and the second programmable metallization cell have respective different resistance switching characteristics.

11. The memory device of claim 10, wherein the resistance switching characteristics of the first programmable metallization cell are symmetrical to the resistance switching characteristics of the second programmable metallization cell.

12. The memory device of claim 10, wherein the resistance switching characteristics of the first programmable metallization cell are asymmetrical to the resistance switching characteristics of the second programmable metallization cell.

13. The memory device of claim 1, wherein the resistance switching device includes first and second memory structures.

14. The memory device of claim 13, wherein the first memory structure includes one of an RRAM, an MRAM, and an FRAM.

15. The memory device of claim 1, wherein the transistor includes a floating gate.

16. A memory device comprising:

a plurality of bit lines;

a plurality of word lines;

a first memory string comprising a first group of memory cells;

a second memory string comprising a second group of memory cells; and

a common source line connected to the first and second memory strings;

wherein the first and second memory strings are connected to respective bit lines;

wherein the word lines are connected to respective memory cells of the first group of memory cells and to respective memory cells of the second group of memory cells;

wherein the first group of memory cells includes a first memory cell connected between the common source line and a first bit line of the plurality of bit lines, the first memory cell comprising;

a first transistor having a first terminal, a second terminal, and a gate terminal, the first transistor being configured to be switchable between a plurality of different threshold voltages associated with respective memory states; and

a first resistance switching device connected in parallel with the first transistor such that the first resistance switching device is connected to the first and second terminals of the first transistor, the first resistance switching device being configured to be switchable between a plurality of different resistances associated with respective memory states.

17. The memory device of claim 16, wherein the gate terminal of the first transistor is connected to a first word line of the plurality of word lines.

18. The memory device of claim 16, wherein the first bit line and the common source line can be controlled for storing data to the first transistor and for storing data to the first resistance switching device.

19. The memory device of claim 16, wherein the first bit line and the common source line can be controlled for reading data from the first transistor and for reading data from the first resistance switching device.

20. The memory device of claim 16, wherein the first resistance switching device includes first and second interface regions having respective different resistance switching characteristics.

21. The memory device of claim 20, wherein at least one of the first and second interface regions includes at least a portion of a tungsten oxide layer.

22. The memory device of claim 16, wherein the first resistance switching device includes a first programmable metallization cell.

23. The memory device of claim 22, wherein the first resistance switching device includes a second programmable metallization cell.

24. The memory device of claim 23, wherein the first programmable metallization cell includes a first solid electrolyte layer and the second programmable metallization cell includes a second solid electrolyte layer.

25. The memory device of claim 16, wherein the first resistance switching device includes first and second memory structures.

26. The memory device of claim 25, wherein the first memory structure includes one of an RRAM, an MRAM, and an FRAM.

27. The memory device of claim 16, wherein the first transistor includes a floating gate.

28. The memory device of claim 16, wherein the second group of memory cells includes a second memory cell connected between the common source line and a second bit line of the plurality of bit lines, wherein the second memory cell comprises a second transistor and a second resistance switching device connected in parallel with the second transistor, wherein the second transistor is configured to be switchable between a plurality of different threshold voltages associated with respective memory states, and wherein the second resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

29. The memory device of claim 28, wherein the first group of memory cells includes a third memory cell connected between the common source line and the first bit line, wherein the third memory cell comprises a third transistor and a third resistance switching device connected in parallel with the third transistor, wherein the third transistor is configured to be switchable between a plurality of different threshold voltages associated with respective memory states, and wherein the third resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

30. The memory device of claim 29, wherein the second transistor is connected in series with the third transistor and the third resistance switching device, and wherein the second resistance switching device is connected in series with the third transistor and the third resistance switching device.

31. A method of reading a memory cell of a semiconductor memory device, the method comprising:

detecting a threshold voltage of a transistor of the memory cell, the transistor being configured to be switchable between a plurality of threshold voltages associated with respective memory states; and

detecting a resistance of a resistance switching device of the memory cell, the resistance switching device being connected in parallel with the transistor and being configured to be switchable between a plurality of resistances associated with respective memory states.

32. The method of claim 31, wherein the detecting of the threshold voltage of the transistor includes applying a first voltage to a gate terminal of the transistor and applying a second voltage across a source and drain of the transistor memory cell such that current flows through the resistance switching device if the first voltage is not sufficient to turn on the transistor.

33. The method of claim 31, wherein the detecting of the resistance of the resistance switching device includes turning off the transistor.

34. A method of programming a memory array, the memory array comprising a plurality word lines and a plurality bit lines, the method comprising:

applying a first voltage to the plurality of word lines except a selected word line; and

applying a second voltage to one selected bit line, wherein a memory element above the selected word line and coupled to the selected bit line is programmed.

35. The method of claim 34, wherein the memory element is one of first and second memory elements of a memory cell of the memory array.

36. The method of claim 35, wherein the first memory element comprises a resistance switching device.

37. The method of claim 36, wherein the second memory element comprises a transistor.

38. The method of claim 37, wherein the first and second memory elements are connected in parallel.