Stacked Memory Devices And Method Of Manufacturing The Same

• US 20110286275A1
• Filed: 05/20/2011
• Published: 11/24/2011
• Est. Priority Date: 05/24/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ho-jung, Jeon, Sang-hun
• Granted Patent: US 8,680,605 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.

Claims

1. A stacked memory device comprising:

at least one memory unit; and

at least one peripheral circuit unit arranged at least one of above and below the at least one memory unit,

wherein the at least one memory unit includes

a memory string array, the memory string array including a plurality of memory strings arranged in a matrix, each of the memory strings including a plurality of memory cells and a string selection device arranged perpendicular to a substrate,

a plurality of bit lines, the plurality of bit lines extending in a first direction and connected to ends of the plurality of memory strings; and

a plurality of string selection pads, the plurality of string selection pads being arrayed in a single line along the first direction and connected to the string selection devices included in the plurality of memory strings.

2. The stacked memory device of claim 1, wherein

the string selection devices are spaced apart in the first direction and a second direction that is perpendicular to the first direction and the string selection devices adjacent to one another in the first direction are connected to different string selection pads of the plurality of string selection pads and the string selection devices adjacent to one another in the second direction are commonly connected to one of the plurality of string selection pads.

3. The stacked memory device of claim 1, wherein

ends of the memory strings of the memory string array that are adjacent to one another in the first direction are commonly connected to one of the plurality of bit lines, and

ends of the memory strings of the memory string array that are adjacent to one another in a second direction perpendicular to the first direction are connected to different bit lines from among the plurality of bit lines.

4. The stacked memory device of claim 1, wherein the at least one memory unit further includes a plurality of word lines connected to the plurality of memory cells, the plurality of word lines extending in the first direction.

5. The stacked memory device of claim 4, wherein the memory string array further includes

a plurality of semiconductor pillars perpendicular to the substrate,

a plurality of storage mediums on sidewalls of the plurality of semiconductor pillars, and

a plurality of gate electrodes above the substrate extending in a direction parallel to the substrate so as to cross the plurality of semiconductor pillars, and further extending in a second direction perpendicular to the first direction.

6. The stacked memory device of claim 5, wherein the plurality of gate electrodes includes

string selection gate electrodes connected to the string selection devices included in the plurality of memory strings;

and

control gate electrodes connected to the plurality of memory cells included in the plurality of memory strings.

7. The stacked memory device of claim 6, wherein the at least one memory unit further includes

a plurality of first contact plugs on ends of the string selection gate electrodes, the plurality of first contact plugs connecting the plurality of string selection pads to the string selection gate electrodes, and

a plurality of second contact plugs on ends of the control gate electrodes, the plurality of second contact plugs connecting the plurality of word lines to the control gate electrodes.

8. The stacked memory device of claim 6, wherein

the control gate electrodes include control gate electrodes at a same level and control gate electrodes at different levels, the control gate electrodes at the same level being commonly connected to one of the plurality of word lines and the control gate electrodes at the different levels being connected to different word lines from among the plurality of word lines.

9. The stacked memory device of claim 6, wherein

each of the memory strings further includes a ground selection device, and

the plurality of gate electrodes further includes ground selection gate electrodes connected to the ground selection devices.

10. The stacked memory device of claim 9, wherein the at least one memory unit further includes a ground selection line connected to the ground selection devices, the ground selection line extending in the first direction.

11. The stacked memory device of claim 10, wherein the at least one memory unit further includes a plurality of third contact plugs on ends of the ground selection gate electrodes, and the plurality of third contact plugs connects the ground selection line to the ground selection gate electrodes.

12. The stacked memory device of claim 10, wherein the at least one memory unit further includes a common source line between the substrate and the plurality of memory strings, the common source line being connected to the plurality of memory strings and extending in the second direction.

13. The stacked memory device of claim 9, wherein ends of the plurality of gate electrodes are step-shaped.

14. The stacked memory device of claim 1, wherein the plurality of memory strings include a plurality of NAND flash memory strings, and the plurality of memory cells include a plurality of NAND flash memory cells.

15. The stacked memory device of claim 4, wherein the at least one peripheral circuit unit includes at least one of

a first circuit unit above a portion of the plurality of bit lines,

a second circuit unit above a portion of the plurality of string selection pads, and

a third circuit unit above a portion of the plurality of word lines.

16. The stacked memory device of claim 15, wherein

the first circuit unit includes at least one of a column decoder, a write driver,

a sense amplifier, and a page buffer,

the second circuit unit includes at least one of a string selection driver and a string selection decoder, and

the third circuit unit includes at least one of a row driver and a row decoder.

17. The stacked memory device of claim 1, wherein

the at least one memory unit includes a plurality of memory units stacked on the substrate, and

the at least one peripheral circuit unit includes a plurality of peripheral circuit units alternately stacked with the plurality of memory units.

18. A method of manufacturing a stacked memory device, the method comprising:

forming a plurality of string selection gate electrodes and a plurality of control gate electrodes extending in a first direction on a substrate;

forming a plurality of semiconductor pillars penetrating the plurality of string selection gate electrodes and the plurality of control gate electrodes;

forming a plurality of bit lines connected to ends of the plurality of semiconductor pillars and extending in a second direction perpendicular to the first direction;

forming a plurality of string selection pads in a single line along the second direction, the plurality of string selection pads being connected to ends of the plurality of string selection gate electrodes; and

forming peripheral circuit devices above a portion of the plurality of bit lines and the plurality of string selection pads.

19. The method of claim 18, further comprising:

forming a plurality of word lines connected to ends of the plurality of control gate electrodes, and extending in the second direction.

20. The method of claim 18, further comprising:

forming storage mediums at sidewalls of the plurality of semiconductor pillars.