Stacked Memory Devices And Method Of Manufacturing The Same
First Claim
1. A stacked memory device comprising:
- at least one memory unit; and
at least one peripheral circuit unit arranged at least one of above and below the at least one memory unit,wherein the at least one memory unit includesa memory string array, the memory string array including a plurality of memory strings arranged in a matrix, each of the memory strings including a plurality of memory cells and a string selection device arranged perpendicular to a substrate,a plurality of bit lines, the plurality of bit lines extending in a first direction and connected to ends of the plurality of memory strings; and
a plurality of string selection pads, the plurality of string selection pads being arrayed in a single line along the first direction and connected to the string selection devices included in the plurality of memory strings.
1 Assignment
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Accused Products
Abstract
A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.
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Citations
20 Claims
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1. A stacked memory device comprising:
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at least one memory unit; and at least one peripheral circuit unit arranged at least one of above and below the at least one memory unit, wherein the at least one memory unit includes a memory string array, the memory string array including a plurality of memory strings arranged in a matrix, each of the memory strings including a plurality of memory cells and a string selection device arranged perpendicular to a substrate, a plurality of bit lines, the plurality of bit lines extending in a first direction and connected to ends of the plurality of memory strings; and a plurality of string selection pads, the plurality of string selection pads being arrayed in a single line along the first direction and connected to the string selection devices included in the plurality of memory strings. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of manufacturing a stacked memory device, the method comprising:
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forming a plurality of string selection gate electrodes and a plurality of control gate electrodes extending in a first direction on a substrate; forming a plurality of semiconductor pillars penetrating the plurality of string selection gate electrodes and the plurality of control gate electrodes; forming a plurality of bit lines connected to ends of the plurality of semiconductor pillars and extending in a second direction perpendicular to the first direction; forming a plurality of string selection pads in a single line along the second direction, the plurality of string selection pads being connected to ends of the plurality of string selection gate electrodes; and forming peripheral circuit devices above a portion of the plurality of bit lines and the plurality of string selection pads. - View Dependent Claims (19, 20)
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Specification