3D TWO-BIT-PER-CELL NAND FLASH MEMORY

• US 20110286283A1
• Filed: 05/21/2010
• Published: 11/24/2011
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wang, Tien-Yen, Lai, Erh-Kun, Shih, Yen-Hao, Lue, Hang-Ting, LUNG, HSIANG-LAN, Lee, Ming Hsiu
• Granted Patent: US 8,437,192 B2
• Time in Patent Office: Days
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

Claims

1. A memory device, comprising:

a plurality of bit lines over a substrate;

a plurality of memory cells over the plurality of bit lines, wherein at least one memory cell of the plurality of memory cells is over another one memory cell of the plurality of memory cells; and

a source plane over the plurality of memory cells.

2. The memory device of claim 1, comprising:

bottom and top memory cubes including respective arrays of semiconductor pillars, a given semiconductor pillar in each array of semiconductor pillars including a plurality of dielectric charge trapping structures in a NAND string along a side of the given semiconductor pillar, and word lines orthogonal to the semiconductor pillars and adjacent the charge trapping structures of the semiconductor pillars, the bottom memory cube including said plurality of memory cells;

the source plane being between the bottom and top memory cubes, the source plane selectively coupled to top ends of each of the semiconductor pillars of the bottom memory cube by a bottom set of source plane select transistors, and selectively coupled to bottom ends of each of the semiconductor body pillars of the top memory cube by a top set of source plane select transistors;

a bottom set of pillar select transistors to selectively couple bottom ends of the semiconductor pillars of the bottom memory cube to corresponding bit lines in said plurality of bit lines; and

a top set of pillar select transistors to selectively couple top ends of the semiconductor pillars of the top memory cube to corresponding bit lines in a plurality of top bit lines.

3. The memory device of claim 2, wherein the given semiconductor pillar in each array of semiconductor pillars comprises a plurality of two-cell unit structures, the two-cell unit structures of the given semiconductor pillar including a first dielectric change trapping structure along a first side of the given semiconductor pillar, and a second dielectric charge trapping structure along a second opposing side of the given semiconductor pillar, such that the first charge trapping structures in the two-cell unit structures of the given semiconductor pillar are arranged in a first NAND string, and the second charge trapping structures in the two-cell unit structures of the given semiconductor pillar are arranged in a second NAND string.

4. The memory device of claim 3, wherein said word lines include a plurality of pairs of word lines arranged orthogonal to one of the arrays of semiconductor pillars, a given pair of word lines including:

a first set of word lines commonly coupled to one another and adjacent the first dielectric charge trapping structures between alternating rows of semiconductor pillars in said one of the arrays of semiconductor pillars; and

a second set of word lines commonly coupled to one another and interleaved with the word lines in the first set of word lines, the second set of word lines adjacent the second dielectric charge trapping structures between interleaved alternative rows of semiconductor pillars.

5. The memory device of claim 2, wherein the dielectric charge trapping structures in the plurality of dielectric charge trapping structures including a tunneling layer adjacent a corresponding word line in said word lines, and a dielectric charge trapping layer between the tunneling layer and a blocking layer, the blocking layer between the dielectric charge trapping layer and the given semiconductor pillar.

6. The memory device of claim 5, further comprising a controller to program and erase selected memory cells by biasing corresponding semiconductor pillars and corresponding word lines to induce Fowler-Nordheim tunneling from the word lines through the tunneling layer to the dielectric charge trapping structures.

7. The memory device of claim 2, including decoder circuitry, the decoder circuitry including:

a row decoder coupled to the bottom and top bit lines and arranged to access individual rows of semiconductor pillars;

a column decoder coupled to the bottom and top sets of pillar select transistors and arranged to access individual columns of semiconductor pillars;

a source plane decoder coupled to the bottom and top sets of source plane select transistors and arranged to access one of the bottom and top memory cubes; and

a fifth decoder coupled to the word lines, and arranged to drive word lines on selected levels in the semiconductor pillars.

8. The memory device of claim 2, further comprising a third memory cube overlying the top memory cube, the top set of pillar select transistors and the plurality of top bit lines, the third memory cube including a third array of semiconductor pillars including a plurality of dielectric charge trapping structures arranged in NAND strings, and word lines orthogonal to the semiconductor pillars in the third array of semiconductor pillars, and wherein:

the top set of pillar select transistors selectively couple bottom ends of the semiconductor pillars of the third memory cube to corresponding bit lines in the plurality of top bit lines.

9. The memory device of claim 1, comprising:

bottom and top memory cubes including respective arrays of semiconductor pillars, a given semiconductor pillar in each array of semiconductor pillars including a plurality of dielectric charge trapping structures in a NAND string along a side of the given semiconductor pillar, and word lines orthogonal to the semiconductor pillars and adjacent the charge trapping structures of the semiconductor pillars, the top memory cube including said plurality of memory cells;

the source plane overlying the top memory cube, the source plane selectively couple to top ends of the semiconductor pillars of the top memory cube by a top set of source plane select transistors;

a bottom source plane underlying the bottom memory cube, the bottom source plane selectively coupled to bottom ends of the semiconductor pillars of the bottom memory cube by a bottom set of source plane select transistors; and

a set of shared pillar select transistors to selectively couple top ends of the semiconductor pillars of the bottom memory cube and bottom ends of the semiconductor pillars of the top memory cube to corresponding bit lines in the plurality of bit lines.

10. A memory device, comprising:

a first set of select transistors;

a first 3D array of memory cells coupled to the first set of select transistors;

a common source coupled to the first 3D array of memory cells;

a second 3D array of memory cells coupled to the common source, wherein the common source is between the first and second 3D array of memory cells; and

a second set of select transistors coupled to the second 3D array of memory cells.

11. A method for manufacturing a memory device, comprising:

forming a memory cube, comprising;

providing a substrate including a set of pillar select transistors and a plurality of bit lines coupled to the set of pillar select transistors, the substrate having an array of contacts coupled to the set of pillar select transistors;

forming a stack of alternating layers of word line material and insulating material over the array of contacts;

forming trenches in the stack, the trenches exposing respective rows of contacts on the surface of the substrate coupled to the set of pillar select transistors, and having sidewalls exposing word line material in the layers of word line material in the stack;

forming a charge trapping structure, lining the sidewalls of the trenches at least on word line material exposed on sidewalls of the trenches;

forming semiconductor pillars within the trenches over the charge trapping structure, the semiconductor pillars contacting respective contacts in the rows of contacts in the trenches; and

forming insulator columns within the trenches on first and second opposing sides of the semiconductor pillars;

forming a set of source plane select transistors having first conduction terminals coupled to top ends of each the semiconductor pillars of the memory cube, and having gate terminals commonly coupled to one another; and

forming a source plane coupled to second conduction terminals of each source plane select transistor in the set of source plane select transistors.

12. The method of claim 11, wherein said forming semiconductor pillars includes filling the trenches with doped semiconductor material over the charge trapping structure, and then applying a patterned etch process to remove the doped semiconductor material within the trenches to leave said semiconductor pillars.

13. The method of claim 12, wherein said forming insulator columns includes filling regions left by said patterned etch process with insulator material to provide said insulator columns.

14. The method of claim 11, wherein said forming a charge trapping structure includes forming a multilayer stack of dielectric materials on the sidewalls of the trenches, the multilayer stack including a tunneling layer, a charge trapping layer and a blocking layer.

15. The method of claim 14, wherein said tunneling layer is formed adjacent the sidewalls of the trenches.

16. The method of claim 11, wherein said forming trenches includes using a first lithographic mask to define a pattern for the trenches, and said forming semiconductor pillars includes using a second lithographic mask to define a pattern for the semiconductor pillars in the trenches.

17. The method of claim 11, including etching the stack to define left side word line structures including a plurality of word lines between alternating pairs of trenches, and right side word line structures including a second plurality of word lines interleaved with the first plurality of word lines between alternating pairs of trenches.

18. The method of claim 11, further comprising:

forming a second set of source plane select transistors having first conduction terminals to the source plane, having gate terminals having gate terminals commonly coupled to one another, and having second conduction terminals coupled to a second array of contacts; and

forming a second memory cube overlying the second set of source plane select transistors, comprising;

forming a second stack of alternating layers of word line material and insulating material over the second array of contacts;

forming second trenches in the second stack, the second trenches exposing respective rows of contacts in the second array of contacts coupled to the second set of pillar select transistors, and having sidewalls exposing word line material in the layers of word line material in the second stack;

forming a second charge trapping structure, lining the sidewalls of the second trenches at least on word line material exposed on sidewalls of the second trenches;

forming second semiconductor pillars within the second trenches over the second charge trapping structure, the second semiconductor pillars contacting respective contacts in the rows of contacts in the second trenches; and

forming second insulator columns within the second trenches on first and second opposing sides of the second semiconductor pillars.