METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA

• US 20110286656A1
• Filed: 05/25/2011
• Published: 11/24/2011
• Est. Priority Date: 11/18/2005
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Kulkarni, Ashok, Duffy, Brian, Maayah, Kais, Rouse, Gordon
• Granted Patent: US 8,139,843 B2
• Time in Patent Office: Days
• US Class Current: 382/144
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 21/67005 Apparatus not specifically provided for elsewhere processes per se H01L21/30, H01L21/46, H01L23/00; simple temporary support means, e.g. using adhesives, electric or magnetic means H01L21/68, H01L21/302

Abstract

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least to similar. The method further includes storing results of the binning step in a storage medium.

Claims

1. A computer-implemented method for determining a position of inspection data in design data space, comprising:

using a computer system to perform the following steps;

aligning data acquired by an inspection system for alignment sites on a wafer with data for predetermined alignment sites, wherein the data for the alignment sites that is aligned comprises data in each of multiple swaths of inspection data acquired by the inspection system for the wafer, and wherein the alignment sites comprise at least one alignment site in each of the multiple swaths;

determining positions of the at least one alignment site in each of the multiple swaths in design data space based on positions of the predetermined alignment sites in the design data space; and

determining a position of the inspection data in each of the multiple swaths in the design data space based on the positions of the at least one alignment site in each of the multiple swaths in the design data space.

2. The method of claim 1, wherein the method is performed during inspection of the wafer.

3. The method of claim 1, wherein the data for the alignment sites on the wafer comprises scanned images, and wherein the data for the predetermined alignment sites comprises design data.

4. The method of claim 1, wherein the data for the alignment sites on the wafer comprises scanned images, and wherein the data for the predetermined alignment sites comprises design clips.

5. The method of claim 1, wherein the position of the inspection data is determined with sub-pixel accuracy.

6. The method of claim 1, further comprising selecting the predetermined alignment sites from design data for the wafer such that there is at least one predetermined alignment site in each of the multiple swaths.

7. The method of claim 1, wherein said aligning is performed before defect detection for the wafer.

8. The method of claim 1, further comprising determining an offset between the data for the alignment sites on the wafer and the data for the predetermined alignment sites based on said aligning, wherein determining the position of the inspection data is performed using the offset and the positions of the at least one alignment site in each of the multiple swaths in the design data space.

9. The method of claim 1, wherein setup of the method is performed off-tool.

10. The method of claim 1, wherein setup of the method is performed on-tool.

11. The method of claim 1, further comprising selecting the predetermined alignment sites by dividing design data for the wafer into portions that correspond to each of the multiple swaths and searching the design data to identify and select at least one predetermined alignment site in each of the multiple swaths.

12. The method of claim 1, further comprising extracting design clips for the predetermined alignment sites from design data for the wafer and storing the extracted design clips in a file that is used by the inspection system for inspection of the wafer.

13. The method of claim 1, further comprising selecting the predetermined alignment sites using information about one or more optical modes and pixel size to be used by the inspection system for inspection of the wafer.

14. The method of claim 1, further comprising selecting the predetermined alignment sites by pre-processing design data to select predetermined alignment sites that are compatible with the inspection system and an inspection process to be used by the inspection system for the wafer.

15. The method of claim 1, further comprising selecting the predetermined alignment sites by scanning a die row on a wafer using the inspection system and processing each frame of a die to identify unique alignment sites.

16. The method of claim 1, further comprising scanning the wafer using the best imaging mode of the inspection system for inspection to select suitable predetermined alignment sites and revisiting the selected predetermined alignment sites to acquire optical patch images using the mode of the inspection system that provides an image that can be best matched to a simulated image for the predetermined alignment sites or a design clip for the predetermined alignment sites.

17. The method of claim 1, wherein the alignment sites comprise more than one alignment site in each of the multiple swaths.

18. The method of claim 1, wherein the alignment sites comprise more than one alignment site in each of the multiple swaths to correct scaling errors.

19. The method of claim 1, wherein the predetermined alignment sites are selected at a predetermined frequency across a die on the wafer.

20. The method of claim 1, wherein the predetermined alignment sites are distributed over a die on the wafer at a predetermined minimum interval distance.

21. The method of claim 1, further comprising aligning the inspection system to the alignment sites to correct stage positional accuracy, rotational errors, x and y translational errors, scaling errors, or some combination thereof in the inspection system.

22. The method of claim 1, further comprising selecting the predetermined alignment sites to include a set of alignment features that in combination provide sufficient alignment information for said determining the positions of the least one alignment site.

23. The method of claim 1, wherein the inspection system is configured to use a bright field mode for inspection of the wafer.

24. The method of claim 1, wherein the inspection system is configured to use a dark field mode for inspection of the wafer.

25. The method of claim 1, wherein the inspection system is configured to use an electron beam imaging mode for inspection of the wafer.

26. The method of claim 1, further comprising determining a sensitivity for detecting defects on different portions of the wafer based on the position of the inspection data in the design data space, one or more attributes of design data in the design data space, and one or more attributes of the inspection data, wherein the one or more attributes of the inspection data comprise one or more image noise attributes, if one or more defects were detected in the different portions, or some combination thereof.

27. The method of claim 26, wherein the one or more attributes of the design data are selected based on yield criticality of defects previously detected in the different portions, fault probability of the defects previously detected in the different portions, or some combination thereof.

28. The method of claim 1, further comprising determining a sensitivity for detecting defects on different portions of the wafer based on the position of the inspection data in the design data space and a context map, wherein the context map comprises values for one or more attributes of design data for the wafer across the design data space.

29. The method of claim 1, wherein the inspection data comprises data for defects on the wafer, the method further comprising determining positions of the defects in the design data space based on the position of the inspection data in the design data space, determining if the defects are nuisance defects based on the positions of the defects in the design data space and one or more attributes of design data in the design data space, and determining if the defects not determined to be nuisance defects are systematic or random defects based on the one or more attributes of the design data in the design data space.

30. The method of claim 1, wherein the wafer and additional wafers are processed using wafer level process parameter modulation, and wherein the method further comprises detecting defects on the wafer and the additional wafers by comparing inspection data for die on the wafer and the additional wafers to a common standard reference die.

31. A system configured to determine a position of inspection data in design data space, comprising:

a storage medium comprising design data; and

a processor coupled to the storage medium, wherein the processor is configured to;

align data acquired by an inspection system for alignment sites on a

wafer with data for predetermined alignment sites, wherein the data for the alignment sites that is aligned comprises data in each of multiple swaths of inspection data acquired by the inspection system for the wafer, and wherein the alignment sites comprise at least one alignment site in each of the multiple swaths;

determine positions of the at least one alignment site in each of the multiple swaths in design data space based on positions of the predetermined alignment sites in the design data space; and

determine a position of the inspection data in each of the multiple

swaths in the design data space based on the positions of the at least one alignment site in each of the multiple swaths in the design data space.

32. A system configured to determine a position of inspection data in design data space, comprising:

an inspection system configured to acquire data for alignment sites on a wafer and multiple swaths of inspection data for the wafer;

a storage medium comprising design data; and

a processor coupled to the inspection system and the storage medium, wherein the processor is configured to;

align the data for the alignment sites on the wafer with data for predetermined alignment sites, wherein the data for the alignment sites that is aligned comprises data in each of the multiple swaths of the inspection data, and wherein the alignment sites comprise at least one alignment site in each of the multiple swaths;

determine positions of the at least one alignment site in each of the multiple swaths in design data space based on positions of the predetermined alignment sites in the design data space; and

determine a position of the inspection data in each of the multiple swaths in the design data space based on the positions of the at least one alignment site in each of the multiple swaths in the design data space.